Electron beam (EB) metrology of Ge channel gate-all-around (GAA) FET (field effect transistor) was investigated. Ge-GAA FET is one of the promising candidates for high performance pMOS device of future node. Ge is superior to Si in hole mobility which can be enhanced further by applying compressive channel strain in GAA structure with SiGe strain relaxed buffer (SRB). Coincide with this advantage, channel buckling could happen more easily. Thus, a monitoring method of channel buckling is required. Chemical instability of Ge is another issue in fabrication process. It is suspected that EB irradiation during SEM inspection could cause the deterioration of device performance. On this background, following two evaluations were performed. The first one is quantitative evaluation of channel buckling. It is found that the channel buckling can be quantified with a proposed buckling index. The second one is assessment of the EB-induced damage on the electrical properties. The results showed that EB irradiation on Ge channels does not affect the device performance when the device is annealed adequately. In conclusion, EB metrology is effective for the evaluation of channel buckling and applicable to Ge channels without deterioration of the device performance.
Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.
A methodology to evaluate the electrical contact between nanowire (NW) and source/drain in NW FETs was investigated with SEM voltage contrast (VC). The electrical defects are robustly detected by VC. The validity of the inspection result was verified by transmission electron microscope (TEM) physical observations. Moreover, estimation of the parasitic resistance and capacitance was achieved from the quantitative analysis of VC images, which are acquired with different scan conditions of an electron beam (EB). A model considering the dynamics of EB-induced charging was proposed to calculate the VC. The resistance and capacitance can be determined by comparing the model-based VC with experimentally obtained VC. Quantitative estimation of resistance and capacitance would be valuable not only for more accurate inspection but also for identification of the defect point.
A method for the inline measurement of the tunnel oxide–nitride-blocking oxide (ONO) film thickness in 3D-NAND devices was studied. The ONO film, whose thickness is critical to the device properties, cannot be measured with conventional methods because it is deposited on the sidewall of a memory hole. Thus, a method to measure the thickness of this vertical film is required. We propose a critical dimension-scanning electron microscope (CD-SEM) measurement. The film thickness can be obtained by measuring the hole diameter before and after the film deposition. Namely, the decrease in the hole diameter should be twice of the thickness in principle. However, its applicability to the actual 10-nm-thick ONO film has not been verified. In this study, the measurement precision and the validity of the method were examined with actual ONO film in the 3D-NAND test wafers. The results showed excellent precision (0.08 nm) and good consistency with planar transmission electron microscope (TEM) and ellipsometry results. In addition, the method revealed the subnanometer thickness difference depending on the nominal hole diameter and the hole density. It suggests the impact of inhomogeneity in the source gas supply during the film deposition. These results ensure that the method is sufficiently precise for the inline local thickness measurement of the ONO film. With this method, yield and reliability managements in the 3D-NAND device manufacturing would be improved.
A methodology to evaluate the electrical contact between nanowire (NW) and source/drain (SD) in NW FETs was investigated with SEM voltage contrast (VC). The electrical defects were robustly detected by VC. The validity of the inspection result was verified by TEM physical observations. Moreover, estimation of the parasitic resistance and capacitance was achieved from the quantitative analysis of VC images which were acquired with different scan conditions of electron beam (EB). A model considering the dynamics of EB-induce charging was proposed to calculate the VC. The resistance and capacitance can be determined by comparing the model-based VC with experimentally obtained VC. Quantitative estimation of resistance and capacitance would be valuable not only for more accurate inspection, but also for identification of the defect point.
A methodology to evaluate the memory cell property of STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory) with a CD-SEM (Critical Dimension-Scanning Electron Microscope) was proposed. STTMRAM is one of the promising candidates among various emerging memories, owing to its low power consumption, low latency, and excellent endurance. Meanwhile, the major issues of STT-MRAM are its small resistance window and the etching-induced damage during memory pillar formation process. The resistance variability and the damage region should be minimized to achieve the reliable operation and the size scaling. The correlation analysis between the resistance and the physical dimension was performed. It provided quantitative information required for process development and control, such as the size-independent resistance variability, the width of the damaged region, and the origin of the short failures. They are essential for the investigation of the causes for the cell-to-cell resistance variability as well as for the quantification of the damage during etching process.
The miniaturization of semiconductors continues, importance of overlay measurement is increasing. We measured overlay with analysis SEM called Miracle Eye which can output ultrahigh acceleration voltage in 1998. Meanwhile, since 2006, we have been working on SEM based overlay measurement and developed overlay measurement function of the same layer using CD-SEM. Then, we evaluated overlay of the same layer pattern after etching. This time, in order to measure overlay after lithography, we evaluated the see-through overlay using high voltage SEM CV5000 released in October 2016. In collaboration between imec and Hitachi High-Technologies, we evaluated repeatability, TIS of SEM-OVL as well as correlation between SEM-OVL and Opt-OVL in the M1@ADI and V0@ADI process. Repeatability and TIS results are reasonable and SEM-OVL has good correlation with Opt-OVL. By overlay measurement using CV 5000, we got the following conclusions. (1)SEM_OVL results of both M1 and V0 at ADI show good correlation to OPT_OVL. (2)High voltage SEM can prove the measurement capability of a small pattern(Less than 1~2um) like device that can be placed in-die area. (3)"In-die SEM based overlay" shows possibility for high order control of scanner
Proc. SPIE. 10145, Metrology, Inspection, and Process Control for Microlithography XXXI
KEYWORDS: Oxides, Metrology, Logic, Statistical analysis, Etching, Germanium, Resistance, Scanning electron microscopy, 3D metrology, Process control, Critical dimension metrology, Algorithm development, Overlay metrology, Standards development, Back end of line
The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.
With the continuous shrink in pattern size and increased density, overlay control has become one of the most critical issues in semiconductor manufacturing. Recently, SEM based overlay of AEI (After Etch Inspection) wafer has been used for reference and optimization of optical overlay (both Image Based Overlay (IBO) and Diffraction Based Overlay (DBO)). Overlay measurement at AEI stage contributes monitor and forecast the yield after formation by etch and calibrate optical measurement tools. however those overlay value seems difficult directly for feedback to a scanner. Therefore, there is a clear need to have SEM based overlay measurements of ADI (After Develop Inspection) wafers in order to serve as reference for optical overlay and make necessary corrections before wafers go to etch. Furthermore, to make the corrections as accurate as possible, actual device like feature dimensions need to be measured post ADI. This device size measurement is very unique feature of CDSEM , which can be measured with smaller area. This is currently possible only with the CD-SEM. This device size measurement is very unique feature of CD-SEM , which can be measured with smaller area. In this study, we assess SEM based overlay measurement of ADI and AEI wafer by using a sample from an N10 process flow. First, we demonstrate SEM based overlay performance at AEI by using dual damascene process for Via 0 (V0) and metal 1 (M1) layer. We also discuss the overlay measurements between litho-etch-litho stages of a triple patterned M1 layer and double pattern V0. Second, to illustrate the complexities in image acquisition and measurement we will measure overlay between M1B resist and buried M1A-Hard mask trench. Finally, we will show how high accelerating voltage can detect buried pattern information by BSE (Back Scattering Electron). In this paper we discuss the merits of this method versus standard optical metrology based corrections.