For the technology node of 90 nm and below, application of design for manufacturing (DFM) techniques is
indispensable. We proposed the line end extension method for metal layer layouts in mask data preparation for
robustness process, and achieved to reduce systematic yield loss caused by isolated patterns . However, these
lithography friendly design approaches sometimes cannot optimize the chip yield by increase in critical area and
creating a new yield failure mechanism. In order to accurately analyze systematic yield failures and optimize layout to
improve manufacturability, a set of metrics that evaluate the robustness of a layout is needed. We propose the new
method to estimate systematic yield due to lithography variations on the chip layout. Lithography variations are
expressed as a function of focus margin, exposure latitude and overlay misalignment, and marginal patterns at process
corners in the chip layout are extracted. Each process window of the extracted patterns is calculated and common
process window is calculated to achieve the full process window of the concerned patterns. The resulting process
window specifications are used on the full chip to calculate systematic yield. A quantitative result of the comparison of
systematic yield and random yield is shown by this method.
Scaling toward 65 nm and beyond, process variations are increased and influences both functional yield and parametric
yield. The process variations consist of systematic components and random components. Systematic variations are
caused by predictable design and process procedures, therefore systematic variations should be removed from process
corner model for LSI design. With the effect of scaling, print images on a wafer shows complicated distortion. The
method of calculating distorted transistor properties without slicing into individual rectangular transistors has been
previously proposed. Using this calculation method, transistor properties with distortion are able to be calculated,
reduction of transistor property variations is expected. Transistor property variations caused by layout dependence could
be reduced by using OPC with SPICE for each transistor, however, the calculation time of gate length retarget with
SPICE is not realistic. Therefore we have investigated approximation for transistor properties using statistics of gate
length distribution and layout parameters, and found that parameter fitting by average and &sgr; of gate length distribution
of each transistor is useful. According to the results of application to standard cell libraries using OPC with transistor
property estimation, we have achieved that our new OPC reduces threshold voltage and drive current variations greatly
without increasing throughput. It is difficult to suppress variation about all properties without area penalty, however,
property priority required for each transistor is different. Therefore performance improvement of the whole circuit and
chip is possible by the argument of priority between manufacturing engineer and circuit designer or using design intents.
The mainstream of resolution enhancement techniques (RET) to critical layers is model-based optical-proximity-effect-correction (OPC) at the 90-nm node and below. For model-based OPC, the simulation model is calibrated using a test pattern transferred onto the wafer on a best dose and best focus condition, so process variations (i.e. focus, exposure dose, etc) cause pinching or bridging (open or short error), otherwise called a hotspot. The technique of reducing hotspots by sub-resolution assist features (SRAFs) and litho-friendly layout are already proposed. However, these methods sometimes cannot improve hotspots by design layouts or the post-OPC shapes. We have developed the technique which improves hotspots by additional modification to the post-OPC patterns of hotspots.
At deep sub-wavelength nodes, it is difficult to transfer accurate mask pattern onto the wafer. However, actual gate pattern is distorted, and timing analysis tools calculates circuit performance on the assumption that the same gate length exists throughout the whole gate width. We calculated the property of the original 2 dimensional distorted transistor by using distribution of gate length. Firstly, in order to evaluate the accuracy of this approach, we have compared them with experimental results that may influence the 65 nm-node design rule. In the conventional method using a rectangular model, results of transistor properties are different from the experimental values, however, results of this approach can reproduce the experimental results. Secondly, this approach is applied to optimization of layout design and OPC. In order to investigate the influence of circuit performance on a layout design and OPC, we calculated the properties (drive current; Ion and leakage current; Ioff) of each transistor contained in standard cell library which is most referred to in a system LSI. We have investigated 2 layouts and 8 OPCs. According to these results, we find out that optimal OPC differs according to the prioritization of Ion and Ioff, whether it is an N-channel or P-channel, and also by layout. Furthermore relaxation of layout decreases variability of Ion caused by defocus. Moreover, since the influence of pattern distortion can be expressed by circuit term such as Ion and Ioff in addition to conventional process terms, it becomes easier for designers to understand manufacturing issues.
Application of DFM (Design for Manufacturability) techniques to the design of random logic metal-layers with million nodes is indispensable for manufacturing semiconductor devices with the node of 90 nm and the bellow. Critical dimension lines corresponding to minimum design rules do not have sufficient process margin due to the presence of focus variation of ArF scanner. This often induces resist-line narrowing, which causes circuit-speed degradations and Cu opens, finally leading to serious yield losses. There are numerous studies on techniques to expand the process margin, such as the placement of dummy and assist patterns. However such techniques can not sometimes be applied due to restrictions of design rule. We note that the presence of such augmented patterns increases the wire capacitance and mask TAT (turn around time). We have developed an automatic layout-pattern generation method which extends the line-end of patterns adjacent to isolated patterns. This resulted in a significant improvement of the process margin of isolated patterns.
We have developed a new pattern correction method to improve the uniformity of gate width and thus transistor characteristics. It is well known that the width of the gate pattern as exposed with an alternating phase shift mask (alt-PSM) varies along the gate width direction, owing to the optical-intensity maxima within the phase shifter regions on both sides of the gate. Since the positions of the maxima depend on the shifter height, the pattern pitch and the illumination conditions (σ and NA), the degree of distortion of the gate length also depends on these factors. We have found that the optimal segment size for optical proximity correction (OPC) of gate distortion also depends on the above factors and should be determined by simulation prior to OPC. From our simulations, shorter segments do not necessarily lead to higher correction accuracy, and the optimal size is strongly related to the degree of distortion. Based on these observations, we propose a novel correction method, in which the look-up table of optimal segment size as a function of shifter height and pattern pitch is referred to in the model-based OPC flow. The advantage of the method has been shown by comparing the correction results to those from the ordinary model-based method, with the latter focusing on the line-end regions where the distortion effects are most remarkable.
In order to clarify the direction of the lithography for the 45 nm node, the feasibilities of various lithographic techniques for gate, metal, and contact layers are studied by using experimental data and aerial image simulations. The focus and exposure budget have been determined from the actual data and the realistic estimation such as the focus distributions across a wafer measured by the phase shift focus monitor (PSFM), the focus and exposure reproducibility of the latest exposure tools, and the anticipated 45 nm device topography, etc. 193 nm lithography with a numerical aperture (NA) of 0.93 achieves the half pitch of 70 nm (hp70) by using an attenuated phase shift mask (att-PSM) and annular illumination. 193 nm immersion lithography has the possibility to achieve the hp60 without an alternative PSM (alt-PSM). For a gate layer, 50-nm/130-nm line-and-space (L/S) patterns as well as 50 nm isolated lines can be fabricated by an alt-PSM. Although specific aberrations degrade the critical dimension (CD) variation of an alt-PSM, ±2.6 nm CD uniformity (CDU) is demonstrated by choosing the well-controlled projection lens and using a high flatness wafer. For a contact layers, printing 90 nm contacts is very critical by optical lithography even if the aggressive resolution enhancement technique (RET) is used. Especially for dense contact, the mask error factor (MEF) increases to around 10 and practical process margin is not available at all. On the other hand, low-energy electron-beam proximity-projection lithography (LEEPL) can fabricate 80 nm contact with large process margin. As a lithography tool for the contact layers of the 45 nm node devices, LEEPL is expected to replace 193 nm lithography.
We propose a practical method of verifying mask data after optical proximity effect correction (OPC). The procedure is as follows. 1) Perform OPC using two tools that have different algorithms. 2) compare these OPC data dn if any differences are found, proceed to the next step. 3) Screening regions are defined by the original (pre-OPC) layout and the differences in these regions are filtered. Total CPU time for this verification is about 5 hours for a chip with 4 million gates.