For IC design starts below the 20nm technology node, the assist features on photomasks shrink well below 60nm and the printed patterns of those features on masks written by VSB eBeam writers start to show a large deviation from the mask designs. Traditional geometry-based fracturing starts to show large errors for those small features. As a result, other mask data preparation (MDP) methods have become available and adopted, such as rule-based Mask Process Correction (MPC), model-based MPC and eventually model-based MDP.
The new MDP methods may place shot edges slightly differently from target to compensate for mask process effects, so that the final patterns on a mask are much closer to the design (which can be viewed as the ideal mask), especially for those assist features. Such an alteration generally produces better masks that are closer to the intended mask design. Traditional XOR-based MDP verification cannot detect problems caused by eBeam effects. Much like model-based OPC verification which became a necessity for OPC a decade ago, we see the same trend in MDP today.
Simulation-based MDP verification solution requires a GPU-accelerated computational geometry engine with simulation capabilities. To have a meaningful simulation-based mask check, a good mask process model is needed. The TrueModel® system is a field tested physical mask model developed by D2S. The GPU-accelerated D2S Computational Design Platform (CDP) is used to run simulation-based mask check, as well as model-based MDP. In addition to simulation-based checks such as mask EPE or dose margin, geometry-based rules are also available to detect quality issues such as slivers or CD splits. Dose margin related hotspots can also be detected by setting a correct detection threshold.
In this paper, we will demonstrate GPU-acceleration for geometry processing, and give examples of mask check results and performance data. GPU-acceleration is necessary to make simulation-based mask MDP verification acceptable.
The detection and management of mask defects which are transferred onto wafer becomes more important day by day.
As the photomask patterns becomes smaller and more complicated, using Inverse Lithography Technology (ILT) and
Source Mask Optimization (SMO) with Optical Proximity Correction (OPC).
To evaluate photomask quality, the current method uses aerial imaging by optical inspection tools. This technique at
1Xnm node has a resolution limit because small defects will be difficult to detect.
We already reported the MEEF influence of high-end photomask using wide FOV SEM contour data of "E3630
MVM-SEM®" and lithography simulator "TrueMask® DS" of D2S Inc. in the prior paper .
In this paper we evaluate the correlation between our evaluation method and optical inspection tools as ongoing
Also in order to reduce the defect classification work, we can compose the 3 Dimensional (3D) information of defects
and can judge whether repairs of defects would be required.
Moreover, we confirm the possibility of wafer plane CD measurement based on the combination between E3630
MVM-SEM® and 3D lithography simulation.
For the mask making community, maintaining acceptable dose margin has been recognized as a critical
factor in the mask-making process. This is expected to be more critical for 20nm logic node masks and
beyond. To deal with this issue, model-based mask data preparation (MB-MDP) had been presented as a
useful method to obtain sufficient dose margin for these complex masks, in addition to reducing shot
When the MB-MDP approach is applied in the actual mask production, the prediction of the dose margin
and the CD in the finished mask is essential.
This paper describes an improved model of mask process which predicts dose margin and CD in finished
masks better compared with the single Gaussian model presented in previous work. The better predictions
of this simple numerical model are confirmed with simulation by D2S and actual mask written by HOYA
using JEOL JBX-3200MV.
To evaluate photomask quality, the current method uses spatial imaging by optical inspection tools. This technique at 1Xnm node has a resolution limit because small defects will be difficult to extract. To simulate the mask error-enhancement factor (MEEF) influence for aggressive OPC in 1Xnm node, wide FOV contour data and tone information are derived from high precision SEM images. For this purpose we have developed a new contour data extraction algorithm with sub-nanometer accuracy resulting in a wide Field of View (FOV) SEM image: (for example, more than 10um x 10um square). We evaluated MEEF influence of high-end photomask pattern using the wide FOV contour data of "E3630 MVM-SEMTM" and lithography simulator "TrueMaskTM DS" of D2S, Inc. As a result, we can detect the "invisible defect" as the MEEF influence using the wide FOV contour data and lithography simulator.
Dose Margin has always been known to be a critical factor in mask making. This paper describes why the issue is far more critical than ever before with the 20-nm logic node and beyond using ArF Immersion lithography. Model-Based Mask Data Preparation (MB-MDP) had been presented [references] to show shot count improvements for these complex masks. This paper describes that MBMDP also improves the dose margin. The improvement predicted with theoretical simulation with D2S is confirmed by the results of real mask written by JBX-3200MV (JEOL) by HOYA.
Mask Error Enhancement Factor (MEEF) has been a standard measure of mask quality . One of the key
assumptions in the construction of MEEF is that mask CD uniformity is not dependent on the shape of mask
feature and can be considered to be a constant for given mask process. This assumption is no longer valid for
small (<100nm), curvilinear or diagonal features. In this paper we extend definition of MEEF to be valid for all
mask shapes call new metric extended MEEF or eMEEF. We also demonstrate on the example of ILT features that
eMEEF increases predictability of mask and wafer CD uniformity sometimes changing overall conclusion about
In writing 22nm logic contacts with 193nm immersion, curvilinear sub-resolution assist features will be desirable on
masks. Curvilinear sub-resolution assist features are good for high volume chips where the wafer volume outweighs
considerations for mask write times. For those chips, even 40 hour write times are tolerated for mask writing. For
lower-volume production of SOC designs, such write times are economically unacceptable. 8 to 12 hours of write times
are feasible for these designs. Previous papers at 2010 Photomask Japan described model-based mask data preparation
(MB-MDP) techniques using circular apertures on production e-beam writers writing curvilinear ideal ILT patterns that
reduced e-beam write-times by nearly a factor of two over conventional approach writing Manhattanized ILT patterns.
This puts the curvilinear assist features within the realm of high-volume production. However, the write times are still
too long for SOC designs. This paper describes a new technique that reduces mask write time further. Resist-exposed
SEM images will be shown, written by JEOL JBX-3200MV. E-beam shot count comparisons for an ideal ILT mask
pattern will be made with the conventional methods, demonstrating a 44% decrease in blanking time. In addition, a
comparison study is shown indicating that an ideal ILT mask pattern that would take 63 hours with conventional
fracturing can be written in about 14 hours using MB-MDP. AIMS projected images demonstrate the pattern fidelity on