This paper investigates the CD correction methods to obtain better across-wafer CD uniformity (CDU) after etching for
logic devices which have various types of patterns. CD optimization methods are evaluated for contact holes with a
diameter of 46 nm after etching. CD optimization methods with PEB temperature and exposure-dose mapping on a wafer
at a lithography step are examined in detail. Simulation study using a full physical resist model is done to analyze the
detailed effects of each optimization method. The results of the simulation show that better optical and chemical image
gives better CD controllability through pitches for etching CD correction. Simulation results also show that the pitch
with a middle CD sensitivity makes the CD correction sensitivity difference minimum through pitches. From the
simulation, the sensitivity behaviors are found to be relatively similar for both of PEB temperature and dose control.
Rather than sensitivity behavior differences between the two CD control methods, the intra-wafer spatial resolution of
the CD control methods is found to be an important factor for the strategy of CD optimization. Finally, by contact-layer
CD optimization, across-wafer CDUs are improved by more than 50%. The variation in the electric resistance of contacts
is also improved by more than 20%. As a result, the proposed method is found to be effective for CDU improvement of
through-pitch contact-hole patterning for advanced logic device.
This paper tries to clarify the requirements for Source-Mask co-Optimization (SMO) type complex masks for low k<sub>1</sub>
technology nodes using a dedicated test mask. The current status of mask CD requirements and inspection capability for
Free Form (FF) SRAFs which give wider process window are discussed by comparing with Rectangular Shape (RS)
SRAFs. From CD deviation analysis with CD bias change at both main and SRAF patterns, the importance of CD
control at entire SRAF is emphasized although the partial lack of SRAF seems to give less impact on the main pattern
lithography performance. It is also suggested that SRAF printability of FF-SRAF needs to be carefully controlled with
mask bias error consideration. To identify the defects which give impact on litho performance, simulation-based defect
printability prediction (M-LMC) using inspection images is evaluated and found to be an important enabler for complex
mask inspection. The simulation-image based defect analysis helps to reduce the nuisance defects, and greatly saves
analysis time of measurement on Aerial Image Measurement System (AIMS<sup>TM</sup>). To introduce the complex free form
mask into production, mask-writing shot-count reduction is also evaluated. It is shown that fragmentation using Model-
Based (MB) Mask Data Preparation (MDP) effectively reduces the mask writing shot counts with using overlapping of
This paper investigates the application of source-mask optimization (SMO) techniques for 28 nm logic device and
beyond. We systematically study the impact of source and mask complexity on lithography performance. For the source,
we compare SMO results for the new programmable illuminator (ASML's FlexRay) and standard diffractive optical
elements (DOEs). For the mask, we compare different mask-complexity SMO results by enforcing the sub-resolution
assist feature (SRAF or scattering bar) configuration to be either rectangular or freeform style while varying the mask
manufacturing rule check (MRC) criteria. As a lithography performance metric, we evaluate the process windows and
MEEF with different source and mask complexity through different k<sub>1</sub> values. Mask manufacturability and mask writing
time are also examined. With the results, the cost effective approaches for logic device production are shown, based on
the balance between lithography performance and source/mask (OPC/SRAF) complexity.
Through simulation and experiment, we evaluate the performance of process window improvement by source only
optimization, mask only optimization or source mask co-optimization. From the results, we demonstrate that SMO is the
most effective, and free-form source application is also effective. Additionally, it is found that SMO with calibrated
resist model is very predictable. We then show that SMO application provides reasonable process window for 28-nm
node and 22-nm node.
For 32 nm Node Logic Device, we studied the effect of laser bandwidth variation on Optical Proximity Effect (OPE) by
investigating through-pitch critical dimension (CD) performance. Our investigation evaluated CD performance with and
without the application of Sub-resolution Assist Features (SRAF). These results enabled us to determine the Iso-Dense
Bias (IDB), and sensitivity to laser bandwidth, for both SRAF and no-SRAF cases, as well as the impact on Process
Window. From the IDB results we present the required laser bandwidth stability in order to maintain OPE variation
within CD Budget tolerances. We also introduce OPE matching results between different generation Immersion
Lithography exposure tools evaluated for 45nm Node Logic Device.
For 45 nm Node logic devices, we have investigated the impact of laser bandwidth fluctuation on Optical Proximity
Effect (OPE) by evaluating variation in through-pitch critical dimension (CD) performance. In addition, from these
results we have calculated the Iso-Dense Bias (IDB), and determined the sensitivity to laser bandwidth fluctuation. These
IDB results also enable us to present the laser bandwidth stability that is required to maintain a constant OPE. And
finally, we introduce results from an investigation into OPE-matching between different generations of exposure tools,
whereby in addition to laser bandwidth control, tilt-scan methodology was employed.
In this paper we demonstrate the many benefits of using immersion lithography that go beyond depth of focus (DOF)
improvement by comparing several key features of dry and immersion lithography. Immersion lithography improves
critical dimension uniformity (CDU) as well as avoiding the necessity for strong resolution enhancement techniques
(RET) as compared with dry lithography. Thus it is possible to significantly reduce the burden of optical proximity
correction (OPC) work with immersion lithography. With respect to imaging, we studied the sensitivity of the
lithographic performances to aberrations and light source spectral bandwidth E95 fluctuations to highlight the benefits of
immersion lithography. The significant improvements that have been seen in the last year in overlay accuracy, defect
control and focus & leveling accuracy have been considered to be challenges to the realization of immersion lithography
in mass production. Now these challenges have been met for the manufacturing requirements of 55 nm logic devices.
The achievements of immersion lithography include overlay accuracy within 10 nm on resist-to-resist wafers and within
20 nm on production wafers, fewer than 10 defects per wafer, and errors of less than 40 nm in focus & leveling on full
wafers. We have established a top-coat resist process. In conclusion, immersion lithography is the most promising
manufacturing solution for 55 nm node logic devices, providing advantages in CDU control, and equivalent overlay
performance and focus & leveling accuracy to dry ArF, without an increased level of defects. NEC Electronics has
completed development and preproduction of the 55 nm logic device "UX7LS" using immersion lithography and has
established the lithography technology for mass production of the UX7LS this year.
Here we present both simulation and experimental results that show the effect of changes in laser light source bandwidth
(E95) on CD Iso-Dense Bias. For the 55nm Technology Node Device, we have shown that E95 stability of less than
0.11pm is required in order to maintain OPE variation to within 2nm. In addition, we also verified another method to
adjust for OPE variations that occur when E95 fluctuates. The Contrast Adjustment method is an effective function to
adjust for OPE variation due to E95 fluctuation; it has been shown to maintain OPE variation less than 1.5nm.
Furthermore, for the 45nm Technology Node Device, we have demonstrated that E95 stability of less than 0.07pm is
required to maintain OPE variation to within 1nm. The bandwidth performance of the latest laser light source exhibits
E95 stability less than 0.03 pm, thereby showing that the OPE variation due to E95 can be kept to under 1nm.