In this paper, we conduct a comprehensive comparative study of next-generation lithography (NGL) processes
in terms of their line width roughness (LWR) performance. We investigate mainstream lithography options
such as double patterning lithography (DPL), self-aligned double patterning (SADP), and extreme ultra-violet
(EUV), as well as alternatives such as directed self-assembly (DSA) and nano-imprint lithography (NIL). Given
the distinctly different processing steps, LWR arises from different sources for these patterning methods, and a
unified, universally applicable set of metrics must be chosen for useful comparisons. For each NGL, we evaluate
the LWR performance in terms of three descriptors, namely, the variation in RMS amplitude (σ), correlation
length (see manuscript) and the roughness exponent (α).
The correlation length (which indicates the distance along the edge beyond which any two linewidth measurements
can be considered independent) for NGL processes is found to range from 8 to 24 nm. It has been
observed that LWR decreases when transferred from resist into the final substrate and all NGL technology options
produce < 5% final LWR. We also compare our results with 2008 ITRS roadmap. Additionally, for the
first time, spatial frequency transfer characteristics for DSA and SADP are being reported. Based on our study,
the roughness exponent (which corresponds to local smoothness) is found to range from ~0.75-0.98; it is close to
being ideal (α = 1) for DSA. Lastly using EUV as an example, we show the importance of process optimization
as these technologies mature.
The impact of gate line edge roughness (LER) on the performance variability of 32nm double-gate (DG) FinFETs is
investigated using a framework that links device performance to commonly used LER descriptors, namely correlation
length (ξ), RMS amplitude or standard deviation (σ) of the line edge from its mean value, and roughness exponent (α).
This modeling approach is more efficient than Monte-Carlo TCAD simulations, and provides comparable results with
appropriately selected input parameters. The FinFET device architecture is found to be robust to gate LER effects.
Additionally, a spacer-defined gate electrode provides for dramatically reduced variability in device performance
compared to a resist-defined gate electrode, which indicates that gate-length mismatch contributes more to variability in
performance than lateral offset between the front and the back gate.