Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards LWR and pattern collapse improvement [1-10]. TEL has developed a DSA development ecosystem (collaboration with customers, consortia, inspection vendors and material suppliers) to successfully demonstrate directed PS-PMMA DSA patterns using chemo-epitaxy (lift-off and etch guide) and grapho-epitaxy integrations on 300 mm wafers. New processes are being developed to simplify process integration, to reduce defects and to address design integration challenges with the long term goal of robust manufacturability. For hole DSA applications, a wet development process has been developed that enables traditional post-develop metrology through the high selectivity removal of PMMA cylindrical cores. For line/ space DSA applications, new track, cleans and etch processes have been developed to improve manufacturability. In collaboration with universities and consortia, fundamental process studies and simulations are used to drive process improvement and defect investigation. To extend DSA resolution beyond a PS-PMMA system, high chi materials and processes are also explored. In this paper, TEL’s latest process solutions for both hole and line/space DSA process integrations are presented.
Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown
the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards line edge
roughness (LER) and pattern collapse improvement [1-4]. The current challenges for industry adoption are materials
maturity, practical process integration, hardware capability, defect reduction and design integration. Tokyo Electron
(TEL) has created close collaborations with customers, consortia and material suppliers to address these challenges with
the long term goal of robust manufacturability.
This paper provides a wide range of DSA demonstrations to accommodate different device applications. In
collaboration with IMEC, directed line/space patterns at 12.5 and 14 nm HP are demonstrated with PS-b-PMMA
(poly(styrene-b-methylmethacrylate)) using both chemo and grapho-epitaxy process flows. Pre-pattern exposure
latitudes of >25% (max) have been demonstrated with 4X directed self-assembly on 300 mm wafers for both the lift off
and etch guide chemo-epitaxy process flows. Within TEL's Technology Development Center (TDC), directed selfassembly
processes have been applied to holes for both CD shrink and variation reduction. Using a PS-b-PMMA hole
shrink process, negative tone developed pre-pattern holes are reduced to below 30 nm with critical dimension uniformity
(CDU) of 0.9 nm (3s) and contact edge roughness (CER) of 0.8 nm. To generate higher resolution beyond a PS-b-PMMA system, a high chi material is used to demonstrate 9 nm HP line/ space post-etch patterns. In this paper, TEL presents process solutions for both line/space and hole DSA process integrations.
As photomask complexity has increased, mask manufacturing has become significantly more challenging. Tightening specs on defect performance, resolution, and CD control have pushed mask manufacturing to achieve levels that nearly match wafer capabilities. To meet wafer manufacturing needs, mask production requires high yield and quick turn-around time, resulting in an increased demand for very high equipment reliability. In-line resist coating capability is important to meet these demands; both for robust 2nd level phase-shift coating processes, and the enablement of advanced 1st-level process development with new resists and new resist process conditions. Intel Corporation worked with Tokyo Electron Ltd (TEL) to bring one of the first CLEAN TRACK ACT M (ACT M) units through design, acceptance tests and into manufacturing. TEL's CLEAN TRACK ACT M is a resist coating tool based on the CLEAN TRACK ACT12 (ACT 12) wafer manufacturing platform, and contains multiple mask-specific modules including advanced softbake oven units, edge-bead removal modules, and cleaning systems. After setup and optimization, the tool shows impressive performance, (for example, within-plate thickness uniformity of < 8A (3s) for certain processes). The motivation of the tool layout is discussed thoroughly. Elements of the module designs and their performance are shown. The acceptance testing performance is presented and includes: cleaning capabilities, oven performance, thickness performance, coating defect levels and edge bead removal capabilities. Finally, there is a limited discussion of manufacturing performance.