Overlay control is gaining more attention in recent years as technology moves into the 32nm era. Strict overlay
requirements are being driven not only by the process node but also the process techniques required to meet the design
requirements. Double patterning lithography and spacer pitch splitting techniques are driving innovative thinking with
respect to overlay control. As lithographers push the current capabilities of their 193nm immersion exposure tools they
are utilizing newly enabled control 'knobs'. 'Knobs' are defined as the adjustment points that add new degrees of
freedom for lithographers to control the scanner. Expanded control is required as current scanner capabilities are at best
marginal in meeting the performance requirements to support the ever demanding process nodes. This abstract is an
extension of the SPIE 2008 paper in which we performed thorough sources of variance analysis to provide insight as to
the benefits of utilizing high order scanner control knobs . The extension this year is to expand the modeling
strategies and to validate the benefit through carefully designed experiments. The expanded modeling characterization
will explore not only high order correction capabilities but also characterize the use of field by field corrections as a
means to improve the overlay performance of the latest generation of immersion lithography tools. We will explore
various correction strategies for both grid and field modeling using KT Analyzer<sup>TM</sup>.
The industry is facing a major challenge looking forward on the technology roadmap with respect to overlay control.
Immersion lithography has established itself as the POR for 45nm and for the next few nodes. As the gap closes between
scanner capability and device requirements new methodologies need to be taken into consideration. Double patterning
lithography is an approach that's being considered for 32 and below, but it creates very strict demands for overlay
performance. The fact that a single layer device will need to be patterned using two sequential single processes creates a
strong coupling between the 1st and 2nd exposure. The coupling effect during the double patterning process results in
extremely tight tolerances for overlay error and scanner capabilities.
The purpose of this paper is to explore a new modeling method to improve lithography performance for the 32nm node.
Not necessarily unique for double patterning, but as a general approach to improve overlay performance regardless of
which patterning process is implemented. We will achieve this by performing an in depth source of variance analysis of
current scanner performance and project the anticipated improvements from our new modeling approach. Since the new
modeling approach will involve 2nd and 3rd order corrections we will also provide and analysis that outlines current
metrology capabilities and sampling optimizations to further expand the opportunities of an efficient implementation of