Comprehensive CD characterization of low-k trench etch for 65nm nodes are performed through a specially
designed mask with global pattern density (GPD) in the range from 25% to 60%. Unlike traditional means, through this
mask we systematically demonstrate global pattern density effects on etch behaviors in correlation with CD uniformity,
CD proximity, and CD linearity without local etch loading effect contributed from nearby environment [1-3] and
position dependent effect contributed from resist developing or aberrations of the wafer-imaging lens . From our
study, CD proximity is the most sensitive item. Wider trench shows larger CD variation as compared with narrow trench
when global environment vary. Moreover, we find that low pressure etch conditions in a small chamber volume etcher
exhibits less CD variation of global pattern density effect. On the other hand, pressure in a large chamber volume etcher
provides better tuning capability in the adjustment of CD variation. The results suggest that residence time might be an
influential factor for the GPD dependent CD control.
This work describes a test vehicle design framework, which minimizes the discrepancy among design rule set, tests structure design and testing plan. The framework is composed of the symbolic design rule set, Parametereized-Device, test structure generator, and test vehicle generator. An approach for simplification and consolidation of test structure is proposed to derive the concise test structure library. Finally, implementation of test vehicle is presented.
This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.
The dislocation at the trench corner under Poly mask edges was found to be the major killer of junction leakage in generic logic technology. The impact of the sacrificial oxide (SAC-OX) of the well ion implantation (I/I) module and the source/drain (S/D) I/I to the defect formation are investigated for the first time. The influence on N<SUP>+</SUP>/P-Well junction leakage caused by the I/I sacrificial oxide from the Rapid Thermal Oxidation (RTO) and Furnace Oxidation (FO) are evaluated by using the process monitoring test structures. Based on the analysis of test structures and the yield evaluation of product, the optimized condition is proposed.