The qubit count of superconducting transmon-based quantum processors is steadily increasing. Some processors are already beyond the 100-qubit scale. In order to keep the development cadence of those quantum processors high, the test time per qubit needs to be strongly reduced from days to hours. Here we present a test time study based on extracting a single-qubit fidelity using a randomized benchmarking protocol. We show that more than a dozen other tune-up steps are required before a randomized benchmarking protocol can be executed on a qubit. En bloc, such a structured workflow leads to a test-time of about 20 mins per qubit. By extrapolating, we find that testing single-qubit fidelities on a hecto-qubit scale quantum chip using the randomized benchmarking protocol would take about 2.5 days. Executing the test protocol is furthermore embedded in a total test cycle that takes into account that a chip needs to be inserted, tested, and retrieved from the system, consisting of a cooldown to 20 mK base temperature and afterwards a warmup to ambient conditions. The whole process of chip testing, starting with insertion and ending with the retrieval of the quantum processor under test is estimated to take about a week. Considering the current state of technology, such a cadence in chip testing can be considered high throughput.
The mission of QuTech is to bring quantum technology to industry and society by translating fundamental scientific research into applied research. To this end we are developing Quantum Inspire (QI), a full-stack quantum computer prototype for future co-development and collaborative R&D in quantum computing. A prerelease of this prototype system is already offering the public cloud-based access to QuTech technologies such as a programmable quantum computer simulator (with up to 31 qubits) and tutorials and user background knowledge on quantum information science (www.quantum-inspire.com). Access to a programmable CMOS-compatible Silicon spin qubit-based quantum processor will be provided in the next deployment phase. The first generation of QI’s quantum processors consists of a double quantum dot hosted in an in-house grown SiGe/28Si/SiGe heterostructure, and defined with a single layer of Al gates. Here we give an overview of important aspects of the QI full-stack. We illustrate QI’s modular system architecture and we will touch on parts of the manufacturing and electrical characterization of its first generation two spin qubit quantum processor unit. We close with a section on QI’s qubit calibration framework. The definition of a single qubit Pauli X gate is chosen as concrete example of the matching of an experiment to a component of the circuit model for quantum computation.
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