In this paper, we present a novel unsupervised change detection approach in temporal sets of synthetic aperture radar
(SAR) images using Markovian fusion. This method is carried out within a Markovian framework which combines two
different change detection algorithms to achieve noise removing and spatial information preserving at the same time.
This approach is composed of two steps: 1) two change maps are generated by two distinctive but complementary
approaches respectively; 2) final results are achieved by fusing the two change maps within a Markovian framework. In
the first step, two different thresholding algorithms are selected to get two change maps aimed at speckle noise
removing and spatial contexture preserving respectively; In the second step, a solution to fusion the two change maps
through a Markov random field framework is proposed. The minimization of energy function is carried out through
iterative conditional mode (ICM) algorithm because of its simplicity and moderate computation-consuming.
Experiments results obtained on a SAR data set confirm the effectiveness of the proposed approach. It shows that the
fusion approach based on MRFs model is a promising way of achieving robust unsupervised change detection.
To accelerate media processing, many media enhancement instructions have been adopted into the instruction set of embedded processors. In this paper, a novel method, called interaction between instructions and algorithms (IIA), is proposed to optimize these media enhancement instructions. Based on the analysis for inherent characteristics of video processing algorithms and processor's architecture, three measures are proposed: three single-cycle instructions for manipulation on bit level are implemented to speed up variable-length decoding; a data path is designed to solve data misalignment in SIMD processing instead of software programs; a memory architecture is proposed to support 128-bit word parallel processing. All these suggestions are used in the optimization of an embedded processor, MediaDSP3200 which fuses RISC architecture and DSP computation capability thoroughly and achieves reduced instruction and 64-bit SIMD instruction set with various addressing mode in a unified RISC pipeline stage architecture. Simulation results show that this optimization method can reduce more than 26.4% of clock cycles for VLD, 47.8% for IDCT and 66.8% for MC in real-time processing.
With the pressure from the design productivity and various special applications, original design method for DSP can no longer keep up with the required speed. A novel design method is needed urgently. Intellectual Property (IP) reusing is a tendency for DSP design, but simple plug-and-play IP cores approaches almost never work. Therefore, appropriate control strategies are needed to connect all the IP cores used and coordinate the whole DSP. This paper presents a new DSP design procedure, which refers to System-on-a-chip, and later introduces a novel control strategy named DWC to implement the DSP based on IP cores. The most important part of this novel control strategy, pipeline control unit (PCU), is given in detail. Because a great number of data hazards occur in most computation-intensive scientific application, a new effective algorithm of checking data hazards is employed in PCU. Following this strategy, the design of a general or special purposed DSP can be finished in shorter time, and the DSP has a potency to improve performance with little modification on basic function units. This DWC strategy has been implement in a 16-bit fixed-pointed DSP successfully.