Hotspot management in low k1 lithography is essential for the achievement of high yield in the manufacture of devices. We have developed a mask quality assurance system with hotspot management based on lithography simulation with SEM image edge extraction of actual mask patterns. However, there are issues concerning this hotspot management from the viewpoint of hotspot sampling and turnaround time.
To solve these problems, we modify the mask quality assurance system by introducing dynamic adaptive sampling in which hotspots are sampled depending on actual mask fabrication quality. As a result, producer's and consumer's risks are efficiently reduced, and TAT for mask inspection is also reduced.
Design rules for logic device have been defined by technology requirement like shrink rate of chip area or process
capability of lithography and other processes. However, those rules are usually only for minimum pitches or minimum
sizes of simple layout, such as line and space patterns with enough long common run length, no intermediate corners, no
jogs and no asymmetry patterns. On the other hand, actual chip layout includes many variations of pattern which often
cause trouble in wafer manufacturing process due to their less process capability, would be found far later when the
design rules are fixed. To solve this issue, additional design rules for two-dimensional patterns, such as line-end to lineend
space, are necessary and have been applied into recent design rules. It is hard to check such many variations of
pattern by the experiment with actual wafer, so checking by lithography simulation in advance is very effective way to
estimate and fix design rules for these two dimensional patterns.
To estimate rules with accuracy, and to minimize numbers in each rule for chip area reduction, OPC and RET must be
included in the estimation, particularly for recent low-k1 lithography. However, OPC and RET are also immature in the
early development term, when design rules are necessary for designers to prepare a test mask to develop the device,
process and some parts of circuit. In other words, OPC, RET and design rules have been modified in parallel, sometime
new RET would be required to achieve a rule, sometime the design rules would be required to relax their numbers, and
sometime new design rules would be required to avoid less process capability.
In this paper, we propose the parallel development procedure for OPC, RET and design rules through the actual
development of 45nm node logic device, focused on metal layer which has many pattern variations, and show how to
build the competitive design rules by applying the latest OPC and RET technologies.
Recently, the critical dimension (CD) abnormality due to lens aberrations of exposure tool has become one of the critical issues in production of semiconductor devices. The most remarkable feature of CD abnormality due to lens aberration is asymmetry of symmetric twin pattern. And the asymmetry is only caused by a particular aberration because the influence on CD abnormality of lens aberration depends on the device pattern shape. Therefore, it is important to know the interaction of the device pattern shape with lens aberrations, and to ensure that consideration of the interaction is reflected in the design of device. This paper introduces a pattern design methods robust to lens aberration is based on Zernike Sensitivity (ZS) method. We conclude that our method modifies a pattern sensitive to lens aberration so that it becomes a pattern robust to lens aberration without reduction of the depth of focus (DOF).