We have much difficulty to control critical dimension (CD) uniformity for contact layer by optical proximity effect
correction (OPC) from 65nm node and below. High mask error enhancement factor (MEEF) in contact layer causes
much influence to surrounding layout pattern edges, resulting in long turn-around-time (TAT) from numerous iterations.
Methods using nominal OPC cause CD uniformity to get worse depending on pattern layout because MEEF is not
considered. Some solutions to this problem may be to calculate MEEF at each pattern edge in order to OPC, and then
decide final correction value by using the weight of this MEEF, but additional calculation causes more TAT.
We have developed a new OPC method that could optimize pattern layout for contact layer with short TAT because
no calculation of each MEEF is necessary. We used our new OPC method to 65nm node LSI. With this method, we were
able to control CD uniformity and get good results with no hotspots. Our new OPC method is much useful to OPC for
65nm node and below.
For the technology node of 90 nm and below, application of design for manufacturing (DFM) techniques is
indispensable. We proposed the line end extension method for metal layer layouts in mask data preparation for
robustness process, and achieved to reduce systematic yield loss caused by isolated patterns . However, these
lithography friendly design approaches sometimes cannot optimize the chip yield by increase in critical area and
creating a new yield failure mechanism. In order to accurately analyze systematic yield failures and optimize layout to
improve manufacturability, a set of metrics that evaluate the robustness of a layout is needed. We propose the new
method to estimate systematic yield due to lithography variations on the chip layout. Lithography variations are
expressed as a function of focus margin, exposure latitude and overlay misalignment, and marginal patterns at process
corners in the chip layout are extracted. Each process window of the extracted patterns is calculated and common
process window is calculated to achieve the full process window of the concerned patterns. The resulting process
window specifications are used on the full chip to calculate systematic yield. A quantitative result of the comparison of
systematic yield and random yield is shown by this method.
The mainstream of resolution enhancement techniques (RET) to critical layers is model-based optical-proximity-effect-correction (OPC) at the 90-nm node and below. For model-based OPC, the simulation model is calibrated using a test pattern transferred onto the wafer on a best dose and best focus condition, so process variations (i.e. focus, exposure dose, etc) cause pinching or bridging (open or short error), otherwise called a hotspot. The technique of reducing hotspots by sub-resolution assist features (SRAFs) and litho-friendly layout are already proposed. However, these methods sometimes cannot improve hotspots by design layouts or the post-OPC shapes. We have developed the technique which improves hotspots by additional modification to the post-OPC patterns of hotspots.
Application of DFM (Design for Manufacturability) techniques to the design of random logic metal-layers with million nodes is indispensable for manufacturing semiconductor devices with the node of 90 nm and the bellow. Critical dimension lines corresponding to minimum design rules do not have sufficient process margin due to the presence of focus variation of ArF scanner. This often induces resist-line narrowing, which causes circuit-speed degradations and Cu opens, finally leading to serious yield losses. There are numerous studies on techniques to expand the process margin, such as the placement of dummy and assist patterns. However such techniques can not sometimes be applied due to restrictions of design rule. We note that the presence of such augmented patterns increases the wire capacitance and mask TAT (turn around time). We have developed an automatic layout-pattern generation method which extends the line-end of patterns adjacent to isolated patterns. This resulted in a significant improvement of the process margin of isolated patterns.
Image placement (IP) error of a 1x stencil mask is a concern for proximity electron beam lithography (PEL) when considering its application in the 65 and 45-nm nodes. According to our preliminary overlay budget for the 65-nm node, the global IP over the mask and the local IP within each membrane should be kept less than 10 and 7 nm, respectively to fulfill the total overlay accuracy of 23 nm. In this paper, we demonstrate the mask structure and the data processing method that enables the mask to be fully compatible with the local IP requirement in those technology nodes.