This paper summarizes the development of EUV molecular resists based on fullerene derivatives: the lithographic
evaluation results of EUV resists using a small-field exposure tool (SFET). Moreover this is the first report on the
application of fullerene-based molecular resists to half-pitch (hp) 3x-nm test device fabrication using a full-field
step-and-scan exposure tool (EUV1).
The spacer patterning process is one of the strongest double patterning technology candidates for fabricating 2xnm node
semiconductor devices by ultra-low-k1 lithography. However, a severe problem exists with this process, it has an
excessive number of steps, including resist patterning, core film etching, spacer film deposition, spacer film etchback,
core film removal, and hard mask patterning steps. We devised a simpler process in which a resist pattern is directly used
as the core film pattern and the spacer film is a low-temperature-deposited oxide film that can be fabricated around the
resist pattern without damaging the resist material. Thus, this new process, which we call "resist-core" spacer patterning,
has significantly fewer patterning steps. When we used the new process to fabricate 2xnm node semiconductor devices
with an ArF immersion scanner, two key issues arose. The first issue regarding the controllability of the resist pattern
profile, which can directly affect the spacer film pattern profile, was addressed by applying various resist patterning
conditions such as resist materials, illumination conditions, and bottom anti-reflecting materials. The second issue,
regarding the resist slimming method was addressed by evaluating two alternative techniques, wet slimming and dry
Due to the promising development status of EUVL as a practical lithography technology for the 2x-nm node, we are
continuing to evaluate its process liability using the EUV1 at Selete, which has an Off-Axis illumination capability. The
resolution limit of the EUV1 for L&S patterns is currently 18 nm for dipole illumination, and 16 nm for aggressive
dipole illumination. This study examined the critical points of EUVL for device manufacturing through wafer processes.
The yield obtained from electrical measurements indicates the maturity of the technology, including the resist process,
the tool, and the mask. Optimization of the resist and RIE processes significantly improved the yield. The final yields
obtained from electrical measurements were 100% for hp 30 nm, 70% for hp 28 nm, and 40% for hp 26 nm. These
results demonstrate EUV lithography to be a practical technology that is now suitable for 2x nm semiconductor
A high-resolution EUV exposure tool is needed to facilitate the development of EUV resists and masks. Since the
EUV small-field exposure tool (SFET) has a high numerical aperture (NA = 0.3), low aberration & flare, and excellent
stage stability, it should be able to resolve fine L/S patterns for the half-pitch 22-nm & 16-nm nodes. In this study, we
evaluated the resolution capability of the SFET and obtained 22-nm L/S patterns with x-slit illumination and clear
modulation of 16-nm L/S patterns with x-dipole illumination. The resolution limit of the SFET seems to be about 15 nm.
The main cause of pattern degradation in 16-nm L/S is probably resist blur. To obtain good shapes for this pattern size,
the resist blur of less than 3.5 nm (σ) is required. The use of y-slit illumination was found to reduce the linewidth
roughness (LWR) of resist patterns. Further reduction of the LWR requires a higher image contrast and a smaller flare.
Due to the central obscuration, the image contrast of the SFET is sensitive to the change of pupil fill. The degradation in
the collector & DMT should be reduced to ensure stable aerial images. This work was supported in part by NEDO.
The Selete R&D program evaluates the feasibility of the Extreme ultraviolet (EUV) lithography process for
manufacturing semiconductor devices. We therefore conducted a yield analysis of hp-2x-nm test chips by using the
EUV1 (Nikon) full-field exposure tool. However, the resist performance did not comply with the stringent requirements
of ultimate resolution, sensitivity, and line-width roughness.
We subsequently reported two new Selete standard resists (SSRs), i.e., SSR6 and SSR7. SSR6 is the polymer
resist used in hp-2x-nm test chip evaluation in which an ultimate resolution of 22 nm line-and-space (L/S) pattern was
achieved. SSR7 is the first molecular resist that was evaluated for feasibility at Selete. SSR7 is a fullerene based resist
with strong etching durability. By using this resist, an ultimate resolution of 24 nm L/S pattern was achieved.
We have also evaluated resist processing by using SSRs for hp-2x-nm test chip evaluation. An ultrathin
underlayer was evaluated for the improvement of pattern transferability. This optimized ultrathin underlayer was coated
on the test chip substrate that was devoid of nano-sized-pinholes, and a fine pattern was observed on this ultrathin
underlayer. In the evaluation of the development process, SSRs were evaluated with tetramethylammonium hydroxide
(TMAH) and tetrabutylammonium hydroxide (TBAH) developer solutions. In summary, it was clear that the lithographic
performance improvement varies depending on the type of polymer resist used with a particular developer solution.
Furthermore, a significant improvement in the prevention of pattern collapse was demonstrated using a combination of
the TBAH developer solution and alternative rinse solutions.
Fundamental studies on polymer bounded PAG and polymer - PAG blend type were carried out with the viewpoint of
dissolution property, lithographic performance, and blur. These materials were prepared to be able to directly compare
and to discuss the difference between blend and bounded PAG, with different PAG loading amount. Dissolution
property revealed the clear difference of these materials tendency to the PAG loading amount variation. Lithographic
performance difference corresponds to the dissolution property difference, and there found the strategy to improve
lithographic performance with polymer bounded PAG type resist. Blur study suggests the advantage in polymer bounded PAG in resolution.
This paper summarizes the development of EUV resists based on various new materials: the lithographic evaluation results of EUV resists from resist material manufacturers using the small field exposure tool (SFET). We discuss the screening results of new resin materials based on
calixresorcinarene, "Noria" and fullerene.
Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication.
This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35
nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene
interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack
resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A
multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal-
2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased
corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical
proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm.
The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the
uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL
test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.
The main development issue for EUV resists is how to concurrently achieve high sensitivity, resolution below 22-nm
half-pitch (hp), and low line width roughness (LWR) in the required fine patterns. Sensitivity and resolution continue
to be improved through advances in EUV resist material research. However, through the material-approach, LWR
remains a difficult issue. Thus, LWR-reduction from the point of view of alternative resist processes was investigated.
As a result, LWR improvement was obtained utilizing alternative developer and rinse solutions. However, a difference
in the LWR-reduction effect of these processes depending on the type of resist material used was observed.
In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1)
for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the
printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered,
and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to
the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction
enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask
error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF)
to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with
the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy
(Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm
via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical
properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for
Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography
is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.
Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch
of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography
technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by
means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test
pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by
etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22-
nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on
yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer
process for device manufacture at the 22-nm node and beyond.
Extreme ultraviolet (EUV) lithography is the leading candidate for the manufacture of semiconductor devices at the hp-
22-nm technology node and beyond. The Selete program covers the evaluation of manufacturability for the EUV
lithography process. So, we have begun a yield analysis of hp-2x-nm test chips using the EUV1 full-field exposure tool.
However, the resist performance does not yet meet the stringent requirements for resolution limit, sensitivity, and line
edge roughness. We reported on Selete standard resist 4 (SSR4) at the EUVL Symposium in 2009. Although it has better
lithographic performance than SSR3 does, pattern collapse limits the resolution to hp 28 nm. To improve the resolution,
we need to optimize the process so as to prevent pattern collapse. An evaluation of SSR4 for the hp-2x-nm generation
revealed that a thinner resist and the use of a TBAH solution for the developer were effective in mitigating this problem.
Furthermore, the use of an underlayer and an alternative rinse solution increased the exposure latitude by preventing
pattern collapse when the resist is overexposed. These optimizations improved the resolution limit to hp 22 nm.
The lithography process on topographic substrate is one of the most critical issues for device manufacturing.
Topographic substrate-induced focus variation occurs between top position and bottom position in a layer. That is,
common depth of focus is reduced. This focus variation is sure to ruin the focus budget in low k1 lithography.
From the focus budget of CMOS device, substrate topography is required to be less than 30nm for hp 45-nm
generation devices and less than 15nm for hp 32-nm generation devices.
In this paper, the authors evaluate a novel concept for hp45-nm generation dual damascene layer for global surface
planarization. The novel concept is thin planarization layer with bottom anti-reflecting (BAR) function. This
planarization layer with optical performance is materialized by UV crosslink materials and process. This concept is
expected to lead to a simpler planarization process. Thin planarization layer with BAR function clear BARC layer and
simplifies the etching process.
Our study showed that the planarization performance of UV crosslink layer with 100nm thickness was 20nm
thickness bias between the field area and dense via hole area. This thickness bias achieved the requirement of hp
45nm generation. Furthermore, fine resist pattern was resolved on the planarization layer by the optimization of acid
components and additive.
Line width roughness (LWR) reduction is a critical issue for low k1 ArF immersion lithography. Various approaches
such as materials, exposure technology and the track process have been performed for LWR reduction during
It was reported that the post-development bake process had good performance for LWR reduction (1). However, the
post-development bake process induced large CD change owing to the degradation of large isolated resist pattern.
Therefore post-development process with small iso-dense bias is required in low k1 ArF immersion lithography.
The resist smoothing process is one of the candidates for LWR reduction with small iso-dense bias. This method
whereby the resist pattern surface is partially melted in organic-solvent atmosphere was shown to have a significant
LWR reduction effect on resist patterns. This paper reports on the application of the resist smoothing process to the
ArF immersion resist pattern after development. It was found that the resist smoothing process was effective to reduce
LWR for ArF immersion resist. As a result of LWR trace from after development to after the hard mask etching process,
the effect of LWR reduction with the resist smoothing process continued after the hard mask etching process.
Furthermore CD change of large isolated patterns with the smoothing process was smaller than in the case of post-development
bake process. We confirmed that the resist smoothing process is an effective method for decreasing LWR
in ArF immersion lithography.
Immersion lithography is widely expected to meet the manufacturing requirements of future device nodes. A critical
development in immersion lithography has been the construction of a defect-free process. Two years ago, the authors
evaluated the impact of water droplets made experimentally on exposed resist films and /or topcoat. <sup>(1)</sup> The results
showed that the marks of drying water droplet called watermarks became pattern defects with T-top profile.
In the case that water droplets were removed by drying them, formation of the defects was prevented. Post-exposure
rinse process to remove water droplets also prevented formation of the defects.
In the present work, the authors evaluated the effect of pre- and post-exposure rinse processes on hp 55nm line and
space pattern with Spin Rinse Process Station (SRS) and Post Immersion Rinse Process Station (PIR) modules on an inline
lithography cluster with the Tokyo Electron Ltd. CLEAN TRACK<sup>TM </sup>LITHIUS <sup>TM</sup> i+ and ASML TWINSCAN
XT:1700Fi , 193nm immersion scanner.
It was found that total defectivity is decreased by pre- and post-exposure rinse. In particular, bridge defects and large
bridge defects were decreased by pre- and post-exposure rinse.
Pre- and post-exposure rinse processes are very effective to reduce the bridge and large bridge defects of immersion
In immersion lithography, it is necessary that the surface of wafer has high hydrohybicity in order to prevent the residue of immersion fluid, i.e. pure water, that cause watermark defect. Usage of a cover material film over the resist film is effective to consistent with high hydrohybicity of the surface and high performance of resist film. But it was problem that much pattern deformation defects was observed with the use of an alkali-soluble type cover material film and an immersion exposure tool. As a result of the examination, it was identified that the fraction of film which caused the pattern deformation in the area of several micrometers were the fraction of the cover material. And the fractions of cover coat material were oriented in the coating defects of the cover material film and in the film peeling after scan of the immersion nozzle at the wafer bevel. The coating defects were improved with the chemical of the cover material. An adhesion process was effective to prevent the film peeling of cover material.
In the liquid immersion lithography, uses of the cover material (C/M) films were discussed to reduce elution of resist components to fluid. With fluctuation of exposure tool or resist process, it is possible to remain of waterdrop on the wafer and watermark (W/M) will be made. The investigation of influence of the W/M on resist patterns, formation process of W/M, and reduction of pattern defect due to W/M will be discussed. Resist patterns within and around the intentionally made W/M were observed in three cases, which were without C/M, TOK TSP-3A and alkali-soluble C/M. In all C/M cases, pattern defect were T-topped shapes. Reduction of pattern defects due to waterdrop was examined. It was found that remained waterdrop made defect. It should be required to remove waterdrop before drying, and/or to remove the defect due to waterdrop. But new dry technique and/or unit will be need for making no W/M. It was examined that the observation of waterdrop through the drying step and simulative reproduction of experiment in order to understand the formation mechanism of W/M. If maximum drying time of waterdrop using immersion exposure tool is estimated 90 seconds, the watermark of which volume and diameter are less than 0.02 uL and 350um will be dried and will make pattern defect. The threshold will be large with wafer speed become faster. From result and speculations in this work, it is considered that it will be difficult to development C/M as single film, which makes no pattern defects due to remained waterdrop.
The ammonia durability of the 157-nm lithography resists is still unclear due to the smaller target dimensions, thinner resist films, and variations in base polymer compared to those of 193-nm and 248-nm resists. It has not been determined what ammonia concentrations must be achieved in order to successfully process 157-nm resists. Until now, the ammonia durability of initial 157-nm resists during post exposure delay (PED) and during post coating delay (PCD) was compared to those of 193-nm and 248-nm resists. It was confirmed that all initial 157-nm resists had low ammonia durability. In this paper, the ammonia durability of newly developed 157-nm resists, that have improved transmittance and resolution, was evaluated during PED and PCD. Then, we found that the ammonia durability of these resists were not enough and that the ammonia concentration from exposure to development should be kept under 0.1 ppb. Thermal desorption spectroscopy results showed that resists with lower ammonia durability tended to have more amount of adsorbed ammonia than other resists. Furthermore, the ammonia durability of 157-nm resist couldn’t be improved to the level of that of 193- and 248-nm resist by the adjustment amount of resist additives. Due to the low ammonia durability, it will be necessary to control the ammonia concentration below 0.1 ppb in processing equipment used in 157-nm lithography.
The bilayer process we developed for 157-nm lithography uses a fluorine-containing silsesquioxane-type resist (F-SSQ). Gate fabrication is done by using a F-SSQ(90 nm)/organic film(200 nm)/poly-Si(150 nm)/SiO<sub>2</sub>(10 nm)/Si structure. The organic film works well as an anti-reflecting layer. Using a microstepper with a numerical aperture of 0.90 and optimizing the resist thickness, we made a 50-nm 1:1 line-and-space (L/S) pattern by using an alternative phase-shifting mask and made a 45-nm SRAM by using a chromeless phase lithography mask. Neither resist pattern footing nor undercutting was observed on the organic film. The reactive ion etching (RIE) selectivity between the F-SSQ and the organic film was sufficient (about 7), the resist pattern was transferred to the underlayer, and both 50-nm 1:1 L/S and 45-nm SRAM gate patterns were made using the organic film as an etching mask. Contact hole (C/H) fabrication is done by using a F-SSQ(105 nm)/organic film(400 nm)/tetraethyl orthosilicate (TEOS)-SiO<sub>2</sub>(1200 nm)/Si structure, and we made a 75-nm 1:1 C/H pattern by using the microstepper with a binary mask. The RIE selectivity was sufficient (about 15) for making high-aspect-ratio contact holes, and we made a 75-nm 1:1 C/H pattern in 1200-nm-thick TEOS. This bilayer process is thus promising for making 65-nm-node semiconductor devices.
We investigated resist profile dependence on Exposed Area Ratio (EAR). Using high activation type chemically amplified positive resist, profile changed from T-top to rounded profile with increasing EAR. We thought that this profile change was caused by acid evaporation and re- sticking. To estimate the effect of re-sticking acid, we performed resist sandwich tests. We measured resist thickness loss after PEB and observed resist profile change caused by re-sticking acid. The results thereby obtained suggest the model we propose. To reduce acid evaporation and re-sticking, we tried to use an overcoat layer. The overcoat layer was found to reduce acid evaporation and be useful for reducing resist profile dependence on EAR.
Recently, resist edge roughness with reducing pattern size has become a serious problem. We investigated the roughness of chemically amplified, positive-tone resists, experimentally. To reduce the roughness, we added a quencher with strong basicity to the resist, and observed sub quarter micron nested lines. As a result, the roughness was improved with increasing the quencher concentration, especially in 0.15 micrometers nested line patterns. Adding quencher was not too much effective for the larger size patterns. The acid concentration in resist was increased by adding quencher, because the nominal dose became large by that. It was also indicated experimentally that generated acid concentration at pattern edge was nearly equal to that of quencher at nominal dose. The nominal dose was determined by quencher concentration. We defined effective acid concentration as remaining acid concentration after quenching. This effective acid concentration increased with increasing quencher concentration too. The roughness seemed to be generated when effective acid concentration profile was lowered. It is indicated that the resist edge roughness with reducing pattern size can be expected from its effective acid concentration profile.