We examined two EPL mask fabrication processes to control precisely image placement (IP) on the EPL masks. One is a wafer process using an electrostatic chuck during an e-beam write and another is a membrane process using a mechanical chuck during the e-beam write. In the wafer process, the global IP is corrected during the e-beam write on the basis of the IP data taken with x-y metrology tool. In the membrane process, the global IP is corrected during the e-beam write on the basis of the data taken with the x-y metrology tool and taken in situ with the e-beam writer. The resist and final global IP (3s) of the wafer process is 7.2 nm and 10.6 nm. For the average local IP errors (3s), the local IP of 5.7 nm at the resist step increases to 14.7 nm at the final step due to process-induced distortions. The local IP could be reduced to 6.0 nm by applying the constant scale value to the mask process. In the membrane process, the resist and final global IP (3s) is 15.3 nm and 17.1 nm. With more detectable alignment marks, it would be possible to improve the global IP. For the average local IP errors (3s) of the membrane process, the average resist and final local IP are 6.7 and 7.1 nm which shows no PID. The two approaches proved to control IP more accurately than the conventional one.