Three oscillators are presented for operation in the 23-25 GHz range where consideration is given to noise, frequency, and power effects of different tank sizes and topologies. The circuits in question employ inductor based tanks with negative resistance provided through an emitter degenerated cross-coupled pair, and use emitter degeneration and inductive peaking to provide bandwidth extension within the single stage output buffers. These circuits are implemented in a 0.18 μm SiGe BiCMOS technology with a 54 GHz ft, and use single device stacks to achieve low voltage operation with VDD as low as 900 mV, while consuming as little as 2.25 mW of power.
An integrated 18 GHz double-balanced direct down-conversion mixer and emitter degenerated quadrature VCO is designed and fabricated in IBM 47 GHz ft SiGe BiCMOS process. A novel headroom optimization scheme is proposed to optimize mixer conversion gain and linearity. The mixer uses an LC tank to reduce voltage supply. With a 3.3 V supply voltage the mixer core consumes 16.5mW and the output buffer matched to 50 Ω consumes 33mW. Measurements indicate a conversion gain of 4.5 dB, a double-side band noise figure of 7.1dB, an IIP3 of -1dBm, and 1dB compression point at -12.2dBm output power. The mixer has the best figure-of-merit compared to recently published mixers operating at similar frequencies in a Si-based process. The voltage controlled oscillator uses an emitter degenerated LC oscillator core with both SiGe HBT and CMOS buffers to achieve oscillation providing direct downconversion for the aforementioned mixer. The oscillator has two anti-phase coupled cores to lower the phase noise through frequency locking, the unused output ports terminated with 50 Ω. The two circuits (several variants of each) are integrated monolithically, with an oscillator breakout with a phase noise performance of -99 dBc/Hz (at 1 MHz separation) with 1 GHz tuning range while pulling 19 mA from a 2.5 V rail. The paper will include all the necessary design equations used to optimize both circuits along with comparisons with other published results.
A positive feedback technique is proposed to augment the bandwidth extension achievable using peaking inductors. The technique is based on inductor sharing between consecutive amplifier stages, and it can be effective when used with smaller inductance values compared to traditional inductive peaking. A 40Gb/s two-stage amplifier comprising a differential pair and emitter followers is presented as a practical design example. An expression for the transfer function of the proposed circuit is derived, and its bandwidth and group delay are compared to equivalent amplifiers with inductive peaking and without bandwidth extension. Circuit sensitivity to the inductance value is also considered. The proposed amplifier was implemented in a SiGe BiCMOS process with ƒτ=120GHz and is used as a predriver for a 50Ω buffer. Combined with the buffer, it provides 10dB of gain and consumes 90mW from a 2.5V power supply and 180mW from a 3.3V power supply. Simulations show about 40% bandwidth improvement compared to traditional inductive peaking. Time domain measurements demonstrate 40Gb/s operation with a maximum differential swing of 1.0V p-p and 20-80% transition times of 7-9ps.
A CMOS circuit topology is demonstrated for the amplification of high-frequency AC currents without requiring similar DC current amplification. This technique is useful for current-domain amplification and processing of signals when low DC power consumption is necessary. Large amounts of AC gain can be achieved using this technique without requiring equivalent DC current gain, which would increase power consumption. Two amplifiers designed using this concept are discussed, one based on a standard current mirror architecture and the second using a cascode-type configuration. Measured results and analysis show the efficacy of this technique for the amplification of multi-Gb/s current-domain signals when implemented in a 0.12μm CMOS technology. Single-stage AC current gains of 12dB are achieved with unity DC current gain, while operating from supply voltages less than 1.0V. Temperature stable gain is also achieved.
A novel current-mode transimpedance amplifier (TIA) architecture is proposed for optical receivers. This new architecture, based around the use of a uniquely biased common-base current buffer stage, allows stable, DC coupled TIAs to be designed in bipolar or CMOS processes operating from extremely low supply voltages and using very low levels of power. Noise performance is comparable to that of higher power designs that operate from higher supply rails. Simulation results have been obtained for a 47GHz fT SiGe BiCMOS process and also 0.25μm CMOS.