Dummy fill insertion in Chemical-mechanical Planarization (CMP) can change the coupling and total capacitance of interconnect. Moreover, dishing and erosion phenomena change interconnect cross-sections and hence significantly affect interconnect resistance. This work first studies interconnect parasitic variations due to (1) different fill patterns that are nominally "equivalent" with respect to foundry rules; and (2) dishing and erosion of conductors and dielectric using an accurate density-step-height model for multi-step CMP from the literature. Our results show that for long parallel wires the variation of coupling capacitance between adjacent wires can be up to 25% and 300% for wires that are 3x and 6x minimum space apart respectively, and the variation of total wire capacitance can be more than 10%. We also show that the variation of wire resistance due to dishing and erosion can be over 30%. This work also evaluates how CMP effects (fill insertion, dishing and erosion) impact the achievable delay of buffered global on-chip interconnects. We obtain the delay of buses from accurate SPICE simulations considering CMP-related parasitic variation. Our studies show that the interconnect design considering fill and buffer insertion simultaneously with CMP effects reduces the unit length delay of global interconnect bus by up to 3.3% over the design which does not consider any CMP effects.