Reticle costs are increasing as users tighten specifications to accommodate the shrinking process windows in advanced semiconductor lithography. Tighter specs often drive the use of e-beam based mask processes, which produce better mask pattern acuity than laser-based tools but suffer lower throughput (and thus higher costs). In some cases, such as contacts, the pattern acuity of an e-beam tool does not seem to be required -- but the tight effective CD uniformity typically produced by an e-beam mask writer is still necessary to prevent wafer level defect problems. This presents problems for the maskshop (e.g., low yield and long cycle time) as well as for the fab (more expensive new product introduction, uncertainty in mask delivery). This paper describes the results of qualifying a low cost, high quality mask making process for 90nm wafer production. The process uses a DUV laser-based mask writer to achieve low cost. Wafer photolithography process results using two masks fabricated with different mask making processes are presented, along with comparative electrical performance.
The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.
It is well known that shrinking k1 factors and increasing MEEF are making it more difficult to print contact holes with acceptable latitude and low defectivity. Given the decreasing process latitude this implies, choosing elements of the lithography process independently is becoming less and less of an option. Instead all elements of the lithography process need to be chosen so that a production-worthy process can be rapidly developed. The large number of options available for building a process further complicates the optimization problem. In this study, simulation results are used to explore the tradeoffs between illumination options and reticle substrate choice as applied to contact hole printing. Relative defectivity levels are presented from logic test circuits for selected cases of illumination and reticle type. These selected cases show that what improves defectivity also improves the Normalized Image Log-Slope (NILS). As it has been previously shown that NILS is already an excellent image quality metric NILS improvement will be used as the basis of the work presented in this paper. Extensive simulations will be used to determine the best choice of illumination and mask type to maximize NILS and by implication minimize defect density.
The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.
Contact patterning for advanced lithography generations is increasingly being viewed as a major threat to the continuation of Moore's Law. There are no easy patterning strategies which enable dense through isolated contacts of very small size. Lack of isolated contact focus latitude, high dense contact mask error factor and incredibly low defectivity rate requirements are severe issues to overcome. These difficulties mean that new and complex patterning methods for contacts at the 90nm and 65nm device generations are being considered. One possible option for improving the process window of contact patterning is resist reflow. Resist reflow can supplement almost any other optical extension method for contact lithography. Previous results have shown the significant benefits of this method for CD control on semi-dense and isolated contact for the 100nm device generation. This work extends the previous work by investigating very dense pitch through isolated contact patterning at 193nm low K1 lithography regimes. The encouraging overall CD control and process window of reflowed contacts using the ARCH TIS2000 bilayer resist system is analyzed through pitch for different imaging options. An investigation of the capability of resist reflow in combination with optimized reticle and illumination for the 65nm device generation is also presented as are details of defectivity levels for reflowed contacts on 90nm device products.
It is well known that shrinking k1 factors are making via and contact layers more difficult to print with acceptable latitude and low defectivity. A typical method for improving the common process window is to use embedded attenuated phase shifting masks (EAPSM). However, even with the improved resolution offered by this technology, small deviations in reticle contact size are producing increasingly severe patterning problems - at the extreme, missing contacts. In this study, we conducted an investigation of a production reticle causing repeating wafer defects that passed the reticle manufacturer’s outgoing inspection. We have examined this reticle using a new inspection algorithm that measures reticle contact energy. This technique successfully detected slightly undersized contacts directly corresponding to the coordinates of the repeating wafer defects.
However, the reticle contact energy inspection also detected numerous undersized contacts that were not detected by wafer SEM inspection. We have produced and printed to wafer a test reticle with programmed over and under sized contacts in order to create a new reticle specification to detect defective contacts before they are shipped to the wafer fab.
The challenge is developing imaging solutions for 180 nm trench lithography that provides maximum overlapping process windows for imaging through pitch. The issue has been addressed first; through simulation to optimize illumination, secondly; with experimentation and the collection of data through dose and focus for a number of pitch sequences with several illumination conditions for each CD. Our problem is how to handle the comparison of many ED windows and still be able to determine which set of conditions provide the best result, the POP factor (Pitch Optimization Process) was determined. The authors will review the POP factor to demonstrate a possible new technique in the calculation of multiple pitch ED windows.
The transition from aluminum/oxide to copper/low-k dielectric interconnect technology involves a variety of fundamental changes in the back-end manufacturing process. The most attractive patterning strategy involves the use of a so-called dual inlay approach, which offers lower fabrication costs by the elimination of one inter-level dielectric (ILD) deposition and polish sequence per metal layer. In this paper, the lithographic challenges for dual inlay, including thin-film interference effect, resist bulk effect, and optical proximity effects are reviewed. The use of attenuated phase shift (aPSM) reticles for patterning vias and trenches was investigated, and shown to provide adequate process margin by optimizing the photoresist and exposure tool parameters. Our results indicate that using appropriately sized attenuated phase shift technique increases the photospeed considerably and simultaneously improves the common process window with sufficient sidelobe suppression margin. The cost of ownership tradeoffs between an attenuated PSM I-Line process and a DUV binary process are discussed.