Directed Self-Assembly (DSA) is being extensively evaluated for application in semiconductor process integration.<sup>1-7 </sup>Since 2011, the number of publications on DSA at SPIE has exploded from roughly 26 to well over 80, indicating the groundswell of interest in the technology. Driving this interest are a number of attractive aspects of DSA including the ability to form both line/space and hole patterns at dimensions below 15 nm, the ability to achieve pitch multiplication to extend optical lithography, and the relatively low cost of the processes when compared with EUV or multiple patterning options. <p> </p>Tokyo Electron Limited has focused its efforts in scaling many laboratory demonstrations to 300 mm wafers. Additionally, we have recognized that the use of DSA requires specific design considerations to create robust layouts. To this end, we have discussed the development of a DSA ecosystem that will make DSA a viable technology for our industry, and we have partnered with numerous companies to aid in the development of the ecosystem. This presentation will focus on our continuing role in developing the equipment required for DSA implementation specifically discussing defectivity reduction on flows for making line-space and hole patterns, etch transfer of DSA patterns into substrates of interest, and integration of DSA processes into larger patterning schemes.
Directed Self-Assembly (DSA) is one of the most promising technologies for scaling feature sizes to 16 nm and below.
Both line/space and hole patterns can be created with various block copolymer morphologies, and these materials allow
for molecular-level control of the feature shapes—exactly the characteristics that are required for creating high fidelity
lithographic patterns. Over the past five years, the industry has been addressing the technical challenges of maturing this
technology by addressing concerns such as pattern defectivity, materials specifications, design layout, and tool
requirements. Though the learning curve has been steep, DSA has made significant progress toward implementation
in high-volume manufacturing.
Tokyo Electron has been focused on the best methods of achieving high-fidelity patterns using DSA processing. Unlike
other technologies where optics and photons drive the formation of patterns, DSA relies on surface interactions and
polymer thermodynamics to determine the final pattern shapes. These phenomena, in turn, are controlled by the
processing that occurs on clean-tracks, etchers, and cleaning systems, and so a host of new technology has been
developed to facilitate DSA. In this paper we will discuss the processes and hardware that are emerging as critical
enablers for DSA implementation, and we will also demonstrate the kinds of high fidelity patterns typical of mainstream
Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards LWR and pattern collapse improvement [1-10]. TEL has developed a DSA development ecosystem (collaboration with customers, consortia, inspection vendors and material suppliers) to successfully demonstrate directed PS-PMMA DSA patterns using chemo-epitaxy (lift-off and etch guide) and grapho-epitaxy integrations on 300 mm wafers. New processes are being developed to simplify process integration, to reduce defects and to address design integration challenges with the long term goal of robust manufacturability. For hole DSA applications, a wet development process has been developed that enables traditional post-develop metrology through the high selectivity removal of PMMA cylindrical cores. For line/ space DSA applications, new track, cleans and etch processes have been developed to improve manufacturability. In collaboration with universities and consortia, fundamental process studies and simulations are used to drive process improvement and defect investigation. To extend DSA resolution beyond a PS-PMMA system, high chi materials and processes are also explored. In this paper, TEL’s latest process solutions for both hole and line/space DSA process integrations are presented.
In this paper we report on the patterning challenges for the integration of Spin-Transfer Torque Magneto-Resistive- Random-Access Memory (STT MRAM). An overview of the different patterning approaches that have been evaluated in the past decade is presented. Plasma based etching, wet echting, but also none subtractive pattering approaches are covered. The paper also reports on the patterning strategies, currently under investigation at imec.
Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown
the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards line edge
roughness (LER) and pattern collapse improvement [1-4]. The current challenges for industry adoption are materials
maturity, practical process integration, hardware capability, defect reduction and design integration. Tokyo Electron
(TEL) has created close collaborations with customers, consortia and material suppliers to address these challenges with
the long term goal of robust manufacturability.
This paper provides a wide range of DSA demonstrations to accommodate different device applications. In
collaboration with IMEC, directed line/space patterns at 12.5 and 14 nm HP are demonstrated with PS-<i>b</i>-PMMA
(poly(styrene-b-methylmethacrylate)) using both chemo and grapho-epitaxy process flows. Pre-pattern exposure
latitudes of >25% (max) have been demonstrated with 4X directed self-assembly on 300 mm wafers for both the lift off
and etch guide chemo-epitaxy process flows. Within TEL's Technology Development Center (TDC), directed selfassembly
processes have been applied to holes for both CD shrink and variation reduction. Using a PS-b-PMMA hole
shrink process, negative tone developed pre-pattern holes are reduced to below 30 nm with critical dimension uniformity
(CDU) of 0.9 nm (3s) and contact edge roughness (CER) of 0.8 nm. To generate higher resolution beyond a PS-<i>b</i>-PMMA system, a high chi material is used to demonstrate 9 nm HP line/ space post-etch patterns. In this paper, TEL presents process solutions for both line/space and hole DSA process integrations.
This paper introduces a new technique utilizing a direct current superimposed (DCS) capacitively-coupled plasma (CCP)
to enhance the etch selectivity to EUV resist with decreasing line width roughness (LWR). This new technique includes
chemical and e-beam curing effects. DCS CCP generates ballistic electrons, which reform the chemical structure of
photoresist. This surface modification hardens the photoresist (PR), and enhances the etch selectivity. The PR-hardening
technique also improves the tolerance towards stress by polymer. Hence, a polymer becomes applicable to protect
photoresist, and the etch selectivity increases even more. As a result, this cure can be processed without consuming the
thickness of EUV resist. The mechanism of EUV resist cure is discussed based on the surface analysis. In addition to the
basic physics of PR-hardening, this paper shows the benchmark results between DCS CCP and the conventional curing
techniques by RIE, such as HBr cure and H<sub>2</sub> cure. Several new chemistries were applied to DCS CCP. In consequence,
the PR-hardening by DCS CCP achieved a 33% reduction in LWR at pre-etch treatment, and a 30% reduction during
under layer etch simultaneously maintaining enough thickness of EUV resist.
Directed self-assembly (DSA) has shown the potential to replace traditional resist patterns and provide a lower cost
alternative for sub-20-nm patterns. One of the possible roadblocks for DSA implementation is the ability to etch the
polymers to produce quality masks for subsequent etch processes. We have studied the effects of RF frequency and etch
chemistry for dry developing DSA patterns. The results of the study showed a capacitively-coupled plasma (CCP)
reactor with very high frequency (VHF) had superior pattern development after the block co-polymer (BCP) etch. The
VHF CCP demonstrated minimal BCP height loss and line edge roughness (LER)/line width roughness (LWR). The
advantage of CCP over ICP is the low dissociation so the etch rate of BCP is maintained low enough for process control.
Additionally, the advantage of VHF is the low electron energy with a tight ion energy distribution that enables removal
of the polymethyl methacrylate (PMMA) with good selectivity to polystyrene (PS) and minimal LER/LWR. Etch
chemistries were evaluated on the VHF CCP to determine ability to treat the BCPs to increase etch resistance and feature
resolution. The right combination of RF source frequencies and etch chemistry can help overcome the challenges of
using DSA patterns to create good etch results.
The root causes of issues in state-of-the-arts resist mask are low plasma tolerance in etch and resolution limit in
lithography. This paper introduces patterning enhancement techniques (PETs) by reactive ion etch (RIE) that solve the
above root causes. Plasma tolerance of resist is determined by the chemical structure of resin. We investigated a hybrid
direct current (DC) / radio frequency (RF) RIE to enhance the plasma tolerance with several gas chemistries. The DC/RF
hybrid RIE is a capacitive coupled plasma etcher with a superimposed DC voltage, which generates a ballistic electron
beam. We clarified the mechanism of resist modification, which resulted in higher plasma tolerance<sup></sup>. By applying an
appropriate gas to DC superimposed (DCS) plasma, etch resistance and line width roughness (LWR) of resist were
improved. On the other hand, RIE can patch resist mask. RIE does not only etch but also deposits polymer onto the
sidewall with sedimentary type gases. In order to put the deposition technique by RIE in practical use, it is very
important to select an appropriate gas chemistry, which can shrink CD and etch BARC. By applying this new technique,
we successfully fabricated a 35-nm hole pattern with a minimum CD variation.
We have developed a cost-effective critical dimension (CD) shrink technique that allows all-in-one processing of CD
shrinking, BARC etching, hard mask etching, and resist stripping in a reactive ion etcher (RIE) for the double patterning
(DP) required in the formation of contact and via hole masks with the most critical exposure margins. This CD shrink
technique was successfully applied to achieve a CD shrinkage of 60 nm and a CD uniformity of within 3 nm at 3 sigma
over the wafer surface. We also determined that the CD shrink technique that employs RIE differs from CD shrink by
resolution enhancement lithography assisted by chemical shrink (RELACS)  and low-temperature molecular layer
deposition (MLD) in having an effect of expanding the lithography process window. We successfully applied our
technique to form a 30-nm CD hole pattern with a duty ratio of 1:1.
We have successfully developed a self-limiting chemical dry etch process, associated equipment, and process flow
featuring no use of plasma and no mask bending. In this process and process flow, the system performs mask trimming
for critical dimension (CD) adjustments after hard-mask formation. First, the CD as defined in lithography is directly
transferred by reactive ion etching (RIE) to silicon oxide film that is to become the hard mask. Next, reactive gas is
deposited on the surface of the silicon oxide film at low temperatures and the reaction product is evaporated at high
temperatures. With this process flow, there is no need to trim a mask made of organic materials. As a result, there is no
mask bending and the amount of hard-mask trimming can be set by the amount of gas flow and pressure in the chemical
dry etch process enabling detailed CD control to be performed. The proposed technology means that even higher aspect
ratios in masks and finer CD control can be achieved for processes such as double patterning (DP) and sidewall transfer