A novel timing recovery for read channel systems with asynchronous full-digital architecture is presented. The timing recovery consists of a frequency synthesizer and digital circuits employing an adaptive oversampling rate controller to keep its oversampling rate constant. Therefore, it is no need to change a digital equalizer characteristic even if a data transfer rate varies. Moreover, it controls the power consumption to be adequate at CAV. Since the proposed timing recovery is constructed of full-digital logic, it can realize a robust read channel system in high-speed signal processing and on next generation LSIs.
A novel timing recovery for Read Channel systems is described. This timing recovery employs a phase error calculation procedure, which extends an operating range of a phase comparator by using a feedback cross position control method.