The Self-Aligned Quadruple Patterning (SAQP) process is one of the most suitable techniques for the patterning of under-20 nm half-pitch lines and spaces (L/S) patterns because it requires only one lithography step, resulting in a relatively low process cost. A serious problem when applying the SAQP process to real devices is the printability of defects in the photomask to the wafer because the effect of the mask defects may be enlarged when the defects are transferred to the spacer pattern. In this study, we evaluate the mask defect printability for both opaque and clear defects in the SAQP process in order to clarify the limit size of the defects on the photomask and to clarify whether the acceptable mask defect size given by ITRS was too small. The defect sizes of both the opaque and clear defects were relaxed as the wafer process progressed from lithography to SAQP. The acceptable mask defect size in the SAQP process found to be 70 nm, which is relaxed from that in ITRS2013.
The spacer patterning process is one of the strongest double patterning technology candidates for fabricating 2xnm node
semiconductor devices by ultra-low-k1 lithography. However, a severe problem exists with this process, it has an
excessive number of steps, including resist patterning, core film etching, spacer film deposition, spacer film etchback,
core film removal, and hard mask patterning steps. We devised a simpler process in which a resist pattern is directly used
as the core film pattern and the spacer film is a low-temperature-deposited oxide film that can be fabricated around the
resist pattern without damaging the resist material. Thus, this new process, which we call "resist-core" spacer patterning,
has significantly fewer patterning steps. When we used the new process to fabricate 2xnm node semiconductor devices
with an ArF immersion scanner, two key issues arose. The first issue regarding the controllability of the resist pattern
profile, which can directly affect the spacer film pattern profile, was addressed by applying various resist patterning
conditions such as resist materials, illumination conditions, and bottom anti-reflecting materials. The second issue,
regarding the resist slimming method was addressed by evaluating two alternative techniques, wet slimming and dry
Subsequent to 45 nm node, immersion lithography using topcoat process is approaching its next step for mass
production. However, microfabrication using immersion topcoat leads to increase in cost due to increase in process
steps. In order to deal with this problem, high throughput scanners equipped with a wafer stage which moves at higher
speed are under development. Furthermore, as resist process compatible with such high speed scanners, non-topcoat
resist is available and seems promising in reducing costs of the resist process. Non-topcoat resist contains hydrophobic
additives which are eccentrically located near the film surface. Because non-topcoat resist enables the formation of a
more hydrophobic surface, non-topcoat resist process is more suitable for high-speed scanning than topcoat resist
process. In the topcoat process, the function of topcoat material and resist material is separated. That is, the resist
material and the topcoat material are responsible for lithographic performance and immersion scanning performance,
respectively. However, the non-topcoat resist is expected both performances. That is, the non-topcoat resist are
required a fine resist profile, small LWR, and low development defects at high speed immersion scanning. In this
paper, we report the application of non-topcoat resist in 22 nm node devices. We investigate the influence of
hydrophobic additives on imaging performance in several base polymers. Additionally, the influence of chemical
species, molecular weight and amount of hydrophobic additive are investigated. Scan performance is also estimated by
dynamic receding contact angle using pin scan tool. 22nm node imaging performance is evaluated using Nikon NSRS610C.
The surface characteristics and lithographic performance of non-topcoat resist for 22 nm node devices are
We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure
conditions. The simulation and experimental results indicate that the minimum pitches should be
determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated
feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um<sup>2</sup> area is clearly
resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability.
There is no immersion induced defects.
Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity
control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node
advances. The target of reflectivity control over existent substrate thickness variation is 0.4%, which was estimated from
our dose budget analysis. Then, single BARC process or stacked mask process (SMAP) was selected to each of the
critical layers according to the substrate transparency. Another key issue in terms of material process was described in
this paper, that is spin-on-carbon (SOC) pattern deformation during substrate etch process. New SOC material without
any deformation during etch process was successfully developed for 32nm node stacked mask process (SMAP). 1.3NA
immersion lithography and pattern transfer performance using single BARC
The stacked-mask process (S-MAP) is a tri-level resist process by lithography and dry etching, which consists of thin
resist, spin-on-glass (SOG), and spun-on carbon (SOC). However, as design rules progress below 60nm, two problems
arise in the conventional S-MAP: 1) the deformation of SOC line pattern during SiO<sub>2</sub> reactive ion etching (RIE), 2) the
degradation of lithography performance due to high reflectivity at the interface between resist and SOG in high NA. In
this study, we clarified the origin of the above problems and improved S-MAP materials and processes. Firstly, we
found that the pattern deformation is induced by the inner stress due to volume expansion by fluorination during RIE,
and that the deformation is suppressed by decreasing hydrogen content of SOC. Secondly, we developed new carbon-containing
SOG that coexists with low reflectivity and acceptable etching performance. Using the above SOG and SOC,
we developed a new S-MAP that shows an excellent lithography / etching performance in sub-45nm device fabrication.
Immersion lithography was applied to 45nm node logic and 0.25um<sup>2</sup> ultra-high density SRAM. The predictable enhancement of focus margin and resolution were obtained for all levels which were exposed by immersion tool. In particular, the immersion lithography enabled to apply the attenuating phase shift mask to the gate level. The enough lithography margin for the alternating phase shift mask was also obtained by using not only immersion tool but also dry tool for gate level. The immersion lithography shrunk the minimum hole pitch from 160nm to 140nm. Thus, the design rule for 45nm node became available by using immersion lithography.
In 45nm-node CMOS, the k1 value is around 0.35. In the low-k1 lithography, the robust design for lens aberration and process fluctuation such as mask CD error is required for manufacturing. The technologies of robust design for 45nm-node CMOS are proposed. The alternating phase shift mask has been applied to obtain high accurate CD controllability for gate level. Since the sensitivity to lens aberration is high, design rule is restricted. Immersion lithography with hyper NA over 1.0 is necessary for contact hole level to get large DOF margin. Since the mask enhanced error factor is large, high accurate CD uniformity on mask is necessary. Using hyper NA immersion tool, high density SRAM whose area is 0.25um2 can be clearly resolved.
Recently, gate length variation such as Line Width Roughness (LWR) is severe problem in MPU. The LWR of resist pattern is mainly due to resist material and optical contrast. However it is hard to improve these factors. Many techniques have reported to decrease LWR, but there were no reports which process was more effective for improvement on LWR. Some methods were considered to improve resist roughness. This paper discusses about LWR of ArF resist in gate layer of 65 nm node device. We tied post bake process after development to smooth resist pattern surface by its surface tension. Recess process of resist roughness by using a pattern shrink film was also investigated. LWR’s were 36% and 26% decreased by post baking process and recess process, respectively. Post bake temperature was near resist melting point. From the consideration of thermal flow process, distance of smoothing force by surface tension is considered about several hundreds nm. Pattern shrink film is using acid catalysis reaction, so its distance of smoothing by acid diffusion is considered about one hundred nm. It is considered that effect of post development process is caused by distance of smoothing force. Moreover influence of those processes for lithographic performance will be evaluated.
In the liquid immersion lithography, uses of the cover material (C/M) films were discussed to reduce elution of resist components to fluid. With fluctuation of exposure tool or resist process, it is possible to remain of waterdrop on the wafer and watermark (W/M) will be made. The investigation of influence of the W/M on resist patterns, formation process of W/M, and reduction of pattern defect due to W/M will be discussed. Resist patterns within and around the intentionally made W/M were observed in three cases, which were without C/M, TOK TSP-3A and alkali-soluble C/M. In all C/M cases, pattern defect were T-topped shapes. Reduction of pattern defects due to waterdrop was examined. It was found that remained waterdrop made defect. It should be required to remove waterdrop before drying, and/or to remove the defect due to waterdrop. But new dry technique and/or unit will be need for making no W/M. It was examined that the observation of waterdrop through the drying step and simulative reproduction of experiment in order to understand the formation mechanism of W/M. If maximum drying time of waterdrop using immersion exposure tool is estimated 90 seconds, the watermark of which volume and diameter are less than 0.02 uL and 350um will be dried and will make pattern defect. The threshold will be large with wafer speed become faster. From result and speculations in this work, it is considered that it will be difficult to development C/M as single film, which makes no pattern defects due to remained waterdrop.
A reversed pattern transfer technique combined with ultra thin resist process is discussed. In the reversed pattern transfer technique, first a resist pattern is formed over an organic under layer, next a Water-Soluble Silicone (WSS) is coated on the pattern and recessed by RIE under oxide etching conditions until the top of the resist pattern appears (i.e. the silicone is filled between the resist patterns), and finally, the resist pattern and the under layer is etched by RIE under resist etching conditions, whereby the resist pattern is transferred to the under layer. For the middle imaging layer, cyclic olefin-maleic anhidride (COMA) - acrylate hybrid type ArF photo resist (1250 A thickness) and EB resist (700 A thickness) are used. 70 nm L/S patterns (for EB) and 110 nm L/S patterns (for ArF) were successfully transferred to the under layer using reversed pattern transfer technique.
A material and process development of a tri-level resist system is carried out to introduce the resist system into 130nm and 110nm device fabrication. The tri-level resist system consists of organic films as a bottom layer, spin-on- glass (SOG) as a middle layer and DUV photoresists as a top imaging layer. A wettability and an acidity of the SOG film are adjusted depending on the type of resist materials to obtain a desirable resist profile. The anti-reflective performance of the tri-level resist system is evaluated along with the lithographic performance. A light reflection (reflectivity) in the DUV photoresist film is reduced less than 0.5% for both KrF resist and ArF resist by choosing the nominal thickness of the SOG film and the bottom layer. A conventional DNQ-Novolak type MUV resist is used for the bottom layer in the KrF tri-level resist system. The MUV resist is thermally cured to avoid mixing with the SOG and to increase the optical density at 248nm wavelength. A newly developed spin-on-carbon film is used for the bottom layer in the ArF tri-level resist system. The spin-on-carbon has an excellent dry etch resistance because of its high carbon content (>90%). The dry etch rates of the MUV resist and the spin-on-carbon for CF4/O2/Ar etch chemistry (SiN RIE condition) are 372nm/min and 287nm/min respectively. A pattern transfer using the tri-level resist system is demonstrated for both L/S and hole structures.
A development monitor system capable of highly accurate control of pattern width has been established. This system is composed of a unique monitor pattern on the process wafer, the 0th order diffraction light measuring unit, and the image analysis and process control unit. In the conventional development process in which no monitor system is employed, the CD variation in 200nm line width was about 15nm when +/- 5 percent dose error exist. However, using the new system, 1nm of CD variation was obtained. In this article, a high-sensitivity monitor pattern is proposed and its performance in controlling 200nm line and space patterns in the development process is reported.