This paper presents design and analysis of a 10GHz inductance-capacitance (LC)-Voltage-Controlled Oscillators (VCO)
implemented with a very high quality (Q) factor on-chip Micro-Electro-Mechanical Systems (MEMS) inductor using
0.25μm silicon-on-sapphire (SOS) technology. A new symmetric topology of suspended MEMS inductor is proposed to
reduce the length of the conductor strip and achieve the lowest series resistance in the metal tracks. This MEMS inductor
has been suspended above the high resistivity SOS substrate to minimise the substrate loss and therefore, achieve a very
high Q-factor inductor. A maximum Q-factor of 191.99 at 11.7GHz and Q-factor of 189 at 10GHz has been achieved for
a 1.13nH symmetric MEMS inductor. The proposed inductor has been integrated with a VCO on the same substrate
using the Metal layers in SOS technology removing the need for additional bond wire. The 10GHz LC-VCO has
achieved a phase noise of -116.27dBc/Hz and -126.19dBc/Hz at 1MHz and 3MHz of offset frequency, respectively. It
consumes 4.725mW of power from 2.5V supply voltage while achieving a Figure of Merit (FOM) of -189.5dBc/Hz.
This paper presents design of a Film Bulk Acoustic Wave Resonators (FBARs) consisting of piezoelectric film,
aluminium nitride (AlN) with top and bottom electrodes of ruthenium (Ru). The lumped Butterworth-Van Dyke (BVD)
Circuit model is used to investigate the theoretical harmonic response and extraction equivalent circuit of the FBAR. A
three-dimensional (3D) Finite Element Method (FEM) is used to evaluate the electro-mechanical performance of the
FBAR. The one-dimension (1D) numerical and the 3D FEM simulation results are analysed and compared. The results
show that coupling coefficient (k<sup>2</sup>
<sub>eff</sub>) up to 7.0% can be obtained with optimised thickness ratio of electrode/piezoelectric
layers. A Figure of Merit (FOM) that considers k<sup>2</sup>
<sub>eff </sub> and quality (Q) factor is used for comparison. The area of FBAR is
900μm<sup>2</sup> and the active filter area size of the FBAR filter is 5400μm<sup>2</sup>. The FBAR filter is designed for operation in Kuband
with centre frequency of 15.5 GHz and fractional bandwidth of 2.6%. The proposed FBAR filter has insertion loss
of -2.3dB which will improve the performance of Ku-band transceiver and improve communication range and data rates
in Ku-band communication links.
This paper presents the design and optimisation of three types of high Quality (Q) factor air suspended inductors
(symmetric (a), symmetric (b) and circular), using micro-electro-mechanical systems (MEMS) technology, for 10GHz to
20GHz frequency band. The geometrical parameters of inductor topology, such as outer diameter, the width of metal
traces, the thickness of the metal and the air gap, are used as design variables and their effects on the Q-factor and
inductance are thoroughly analysed. The inductor has been designed on high resistivity Silicon-on-Sapphire (SOS)
substrate in order to reduce the substrate loss and improve the Q factor. Results indicate that the proposed inductor
topology (symmetric (a)) has highest Q-factor with peak Q-factor of 192 at 12GHz for a 1.13nH inductance.
This paper presents the design and implementation of a fully on-chip wideband low noise amplifier (LNA) using 0.25-
micron Silicon-on-Sapphire (SOS) technology for the next-generation Square Kilometre Array (SKA) radio telescope
application. Ultra low noise and wideband operation are the principle design challenges in LNA for SKA application.
The proposed LNA design employs cascaded inductive degeneration architecture and achieves broadband matching by
using on-chip high quality factor (Q) SOS inductors inter-stage/intermediate LC matching circuit. Use of high Q
inductors results in low noise input matching circuit that enables the LNA to achieve the required minimum noise figure
(NF). The proposed LNA is a complete on-chip solution that achieves a NF from 0.57dB to 0.68dB over 1.1GHZ-band
with a minimum gain of 15.3dB. This design consumes only 40.78mW of power from a 2.5-V power supply.
This paper presents an optimised low-power low-phase-noise Voltage Controlled Oscillator (VCO) for Bluetooth
wireless applications. The system level design issues and tradeoffs related to Direct Conversion Receiver (DCR) and
Low Intermediate Frequency (IF) architecture for Bluetooth are discussed. Subsequently, for a low IF architecture, the
critical VCO performance parameters are derived from system specifications. The VCO presented in the paper is
optimised by implementing a novel biasing circuit that employs two current mirrors, one at the top and the other one at
the bottom of the cross-coupled complementary VCO, to give the exact replica of the current in both the arms of current
mirror circuit. This approach, therefore, significantly reduces the system power consumption as well as improves the
system performance. Results show that, the VCO consumes only 281μW of power at 2V supply. Its phase noise
performance are -115dBc/Hz, -130dBc/Hz and -141dBc/Hz at the offset frequency of 1MHz, 3MHz and 5MHz
respectively. Results indicate that 31% reduction in power consumption is achieved as compared to the traditional VCO
design. These characteristics make the designed VCO a better candidate for Bluetooth wireless application where power
consumption is the major issue.
This paper presents a detailed design and analysis of fringing and metal thickness effects in a Micro Electro Mechanical System (MEMS) parallel plate capacitor. MEMS capacitor is one of the widely deployed components into various applications such are pressure sensor, accelerometers, Voltage Controlled Oscillator's (VCO's) and other tuning circuits. The advantages of MEMS capacitor are miniaturisation, integration with optics, low power consumption and high quality factor for RF circuits. Parallel plate capacitor models found in literature are discussed and the best suitable model for MEMS capacitors is presented. From the equations presented it is found that fringing filed and metal thickness have logarithmic effects on capacitance and depend on width of parallel plates, distance between them and thickness of metal plates. From this analysis a precise model of a MEMS parallel plate capacitor is developed which incorporates the effects of fringing fields and metal thickness. A parallel plate MEMS capacitor has been implemented using Coventor design suite. Finite Element Method (FEM) analysis in Coventorware design suite has been performed to verify the accuracy of the proposed model for suitable range of dimensions for MEMS capacitor Simulations and analysis show that the error between the designed and the simulated values of MEMS capacitor is significantly reduced. Application of the modified model for computing capacitance of a combed device shows that the designed values greatly differ from simulated results noticeably from 1.0339pF to 1.3171pF in case of fringed devices.