To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho
model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented
during final routing optimization.
This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow.
The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical
Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho
hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines
to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge
to a clean design.
Automatic layout optimization is becoming an important component of the DfM work flow, as the number of
recommended rules and the increasing complexity of trade-offs between them makes manual optimization increasingly
difficult and time-consuming. Automation is rapidly becoming the best consistent way to get quantifiable DfM
improvements, with their inherent yield and performance benefits for standard cells and memory blocks. Takumi autofixer
optimization of Common Platform layouts resulted in improved parametric tolerance and improved DfM metrics,
while the cell architecture (size and routability) and the electrical characteristics (speed/power) of the layouts remained
intact. Optimization was performed on both GDS-style layouts for standard cells, and on CDBA (Cadence Data Base
Architecture)-style layout for memory blocks. This paper will show how trade-offs between various DfM requirements
(CAA, recommended rules, and litho) were implemented, and how optimization for memories generated by a compiler
was accomplished. Results from this optimization work were verified on 45nm design by model and rule based DfM
checking and by wafer yields.
DFM considerations have become an indispensable and integral part of advanced nanometer semiconductor product
designs. Traditional first-generation DFM tools have focused on functional lithography hotspot detections. While useful,
these tools offer designers few hints on the complex layout fixings and the intricate trade-off decisions required. With
these limitations, DFM layout optimization has become a tedious and inconsistent design endeavor. In addition, the long
and intense calibration cycle required for the traditional DFM models have hindered their effectiveness and timeliness.
An automatic DFM layout optimization system that performs systematic multi-objective functional and parametric DFM
optimizations at early design phase will be introduced. A calibration-lite methodology that has expedited the DFM
model set-ups will be discussed along with the silicon validation test pattern designs. Finally, both simulation and
silicon experiment results will be presented.
SC989: DfM: Profitable Scaling through Design-Technology Co-Optimization
As the need for dimensional scaling continues to outpace the availability of higher resolution patterning solutions, the role of Design for Manufacturability (DfM) is shifting from providing incremental yield enhancement in 65nm and 45nm to becoming the fundamental technology enabler in 32nm and beyond. In parallel, the marketplace and the end customers are demanding high DfM quality at all design levels, from IP components to full chip.
This course will cover the most popular manufacturability analysis techniques and their uses in DfM-enhanced design flows at different design phases. Model-based techniques such as critical area analysis, lithography hotspot detection, and CMP thickness prediction will be contrasted to rules-based techniques such as recommended design rules or enhanced routing rules. Differences between iterative DfM techniques such as process aware layout optimization and prescriptive DfM techniques such as regularized layouts and design aware manufacturing will be discussed. The advantages and challenges of introducing manufacturability knowledge early in the design flow will be compared to those of applying manufacturability considerations late. Finally, the most prominent opportunities for innovation in DfM for technology nodes beyond 65nm will be reviewed.