Improvements in compact lithography models and compute resources have allowed EDA suppliers to keep up with
the accuracy and turnaround time (TAT) requirements for each new technology node. Compact lithography models
are derived from the Hopkins method to calculate the image at the wafer. They consist of the pre-calculated optical
kernel set that includes properties of projection and source optics as well as resist effects. The image at the wafer is
formed by the convolution of optical kernel set with the mask transmission. The compact model is used for optical
proximity correction (OPC) and lithography rule checking (LRC) due to its excellent turnaround time in full chip
applications. Leading edge technology nodes, however, are inherently more sensitive to process variation and
typically contain more low contrast areas, sometimes resulting in marginal hotspots. In these localized areas, it is
desirable to have access to more predictive first principle lithography simulation. The Abbe method for lithography
simulation includes full 3D resist models that solves from first principles the reaction/diffusion equation of the post
exposure bake to provide the highest accuracy. These rigorous models have the ability to provide added insight into
3D developed profile in resist at the wafer level to assist in the application of OPC and disposition of hotspots found
by LRC using compact models. This paper will explore the benefits of a tightly integrated rigorous lithography
simulation during LRC hotspot detection step of the post OPC flow. Multiple user flows will be addressed along
with methods for automating the flows to maximize the imaging predictability where needed while keeping the
impact to turn around time to a minimum.
A new method for simultaneous Source-Mask Optimization (SMO) is presented. In order to produce optimum
imaging fidelity with respect to exposure lattitude, depth of focus (DoF) and mask error enhancement factor
(MEEF) the presented method aims to leverage both, the available degrees of freedom of a pixelated source
and those available for the mask layout. The approach described in this paper is designed as to work with
dissected mask polygons. The dissection of the mask patterns is to be performed in advance (before SMO) with
the Synopsys Proteus OPC engine, providing the available degrees of freedom for mask pattern optimization.
This is similar to mask optimization done for optical proximity correction (OPC). Additionally, however, the
illumination source will be simultaneously optimized. The SMO approach borrows many of the performance
enhancement methods of OPC software for mask correction, but is especially designed as to simultaneously
optimize a pixelated source shape as nowadays available in production environments. Designed as a numerical
optimization approach the method is able to assess in acceptable times several hundreds of thousands source-mask
combinations for small, critical layout snippets. This allows a global optimization scheme to be applied to the
SMO problem which is expected to better explore the optimization space and thus to yield an improved solution
quality compared to local optimizations methods. The method is applied to an example system for investigating
the impact of source constraints on the SMO results. Also, it is investigated how well possibly conflicting goals
of low MEEF and large DoF can be balanced.
It is suggested that stray-light (SL, also called flare, scattered light) impact can be compensated by modifying standard
OPC method. Compared to traditional optical proximity effect caused by diffraction limit, stray light leads to extremely
long range (~ 100 micrometer ~ 10 millimeter) proximity effect. Appropriate approximation is introduced for stray-light
implemented OPC in such a large scale. This paper also addresses other practical problems in the stray-light OPC and
presents how to solve the problems.
The upcoming 45nm and 32nm device generations will continue the familiar industry lithography trends of
decreased production K1 factor, reduced focus error tolerances and increased pattern density. As previous
experience has shown, small changes in the values of lithographic K1, focus tolerance and pattern density
for the process-design space can lead to large required changes in OPC and RET solutions. Therefore,
significant improvements in utility and speed are needed for these new device generations. In this paper we
highlight significant new functionality and performance capabilities using existing Field-based OPC and
RET methods. The use of dense grid calculations in Field-based methods is shown to provide a software
platform for robust and fast implementation of new model-based RET techniques such as model-based
assist feature placement and tuning. We present the performance and capability increases for model-based
RET methods. Additionally, we have studied and present the performance of production 45nm generation
field-based OPC and RET software across several different multiple-purpose hardware platforms.
Significant improvements in runtime (for approximately the same hardware cost) are observed with new
general purpose hardware platforms and with software optimization for this hardware.
The existing approaches to lithography model generation rely heavily on one-dimensional (1D) Scanning Electron Microscope (SEM) measurements to characterize a two-dimensional (2D) process. Traditional 1-D techniques require measuring an exhaustive test cell matrix containing hundreds of features representing different sizes, shapes, and pitches. Despite the large amount of data collected, there can still be a significant amount of model error present, particularly in 2D structures such as line ends and corners, which do not lend themselves to a well defined CD measurement. This is due to the inadequacy of using a 1D measurement for characterizing 2D features. A new approach to lithography simulation confirms the axiom "a SEM image is worth a thousand CD measurements". Using a set of six or fewer SEM images and fitting a contour-based 2-D simulation to the image during the model derivation, achieves a good 2D predictive capability without sacrificing through pitch predictability. This paper will show the results of using SEM images to tune lithography models on clear and dark field layers and illustrate the accuracy of the models using contour based simulations overlaid with SEM images. This approach to OPC modeling greatly reduces the number of CD measurements required to generate a model and lessens the susceptibility of the model to SEM CD metrology errors, while achieving a very well tuned model. This method works best when the 2-D simulation and calibration are coupled to the algorithms that perform the correction.
Production readiness of phase-edge/chromeless reticles employing off-axis illuminations for 65nm node lithography is assessed through evaluation of mask design conversion and critical layer lithography performance. Using ASML /1100ArF scanners, we achieved k1=0.33 for chromeless phase shift mask (crlPSM) with more than 0.6um DOF for dense features. Subresolution assist features allow for acceptable depth of focus through pitch. However, chromeless feature linearity fall-off continues to be a major issue hampering the acceptance of crlPSM for production. Several mask data conversion schemes such as chromeless gratings and chrome patches have been proposed as viable solutions to mitigate the chromeless linearity fall-off issue. We evaluated chromeless gratings, chromeless rims and chrome patches and report on their performance in resolving the chromeless linearity fall-off issues as well as mask process complexity associated with each solution.
For logic design, Chrome-less Phase Shift Mask is one of the possible solutions for defining small geometry with low MEF (mask enhancement factor) for the 65nm node. There have been lots of dedicated studies on the PCO (Phase Chrome Off-axis) mask technology and several design approaches have been proposed including grating background, chrome patches (or chrome shield) for applying PCO on line/space and contact pattern. In this paper, we studied the feasibility of grating design for line and contact pattern. The design of the grating pattern was provided from the EM simulation software (TEMPEST) and the aerial image simulation software. AIMS measurements with high NA annular illumination were done. Resist images were taken on designed pattern in different focus. Simulations, AIMS are compared to verify the consistency of the process with wafer printed performance.
The complexity of current semiconductor technology due to shrinking feature sizes causes more and more engineering efforts and expenses to deliver the final product to customers. One of the largest expense in the entire budget is the reticle manufacturing. With the need to perform mask correction in order to account for optical proximity effects on the wafer level, the reticle expenses have become even more critical. For 0.13um technology one can not avoid optical proximity correction (OPC) procedure for modifying original designs to comply with design rules as required by Front End (FE) and Back End (BE) processes. Once an OPC model is generated one needs to confirm and verify the said model with additional test reticles for every critical layer of the technology. Such a verification procedure would include the most critical layers (two FE layers and four BE layers for the 0.13 technology node). This allows us to evaluate model performance under real production conditions encountered on customer designs. At LSI we have developed and verified the low volume reticle (LVR) approach for verification of different OPC models. The proposed approach allows performing die-to-die reticle defect inspection in addition to checking the printed image on the wafer. It helps finalizing litho and etch process parameters. Processing wafers with overlaying masks for two consecutive BE layer (via and metal2 masks) allowed us to evaluate robustness of OPC models for a wafer stack against both reticle and wafer induced misalignments.
A number of techniques are used for resolution enhancement in leading edge lithography. As feature dimensions shrink, these resolution enhancement techniques (RETs) become more aggressive, causing huge increases in data volume, complexity and write time. The results of these techniques are verified using methods such as SEM measurements of resist or etched structures on the wafer. These RETs tend to either over or under-compensate by way of the suggested corrections or enhancements with respect to the actual device operation. In addition, the systematic and random metrology errors inherent in wafer level top-down SEM measurements become more significant as feature sizes shrink and tolerances become tighter. These errors further cloud the decision as to which RET is most suitable and necessary. To overcome these problems, we have designed an electrical test vehicle which targets those geometries most prevalent in the cells for a given technology. Electrical test (E-test) structures are then varied around these geometries covering the design rule space. Device parameters are measured over this design space for various RETs. This method reconciles the accuracy or effectiveness of RET models using electrical device parameters and uses the same to choose the RET which results in the lowest NRE while at the same time meeting all electrical requirements.
Dark field (i.e. hole and trench layer) lithographic capability is lagging that of bright field. The most common dark field solution utilizes a biased-up, standard 6% attenuated phase shift mask (PSM) with an under-exposure technique to eliminate side lobes. However, this method produces large optical proximity effects and fails to address the huge mask error enhancement factor (MEEF) associated with dark field layers. It also neglects to provide a dark field lithographic solution beyond the 130nm technology node, which must serve two purposes: 1) to increase resolution without reducing depth of focus, and 2) to reduce the MEEF. Previous studies have shown that by increasing the background transmission in dark field applications, a corresponding decrease in the MEEF was observed. Nevertheless, this technique creates background leakage problems not easily solved without an effective opaqueing scheme. This paper will demonstrate the advantages of high transmission lithography with various approaches. By using chromeless dark field scattering bars around contacts for image contrast and chromeless diffraction gratings in the background, high transmission dark field lithography is made possible. This novel layout strategy combined with a new, very high transmission attenuating layer provides a dark field PSM solution that extends 248nm lithography capabilities beyond what was previously anticipated. It is also more manufacturing-friendly in the mask operation due to the absence of tri-tone array features.
We present a comparison of line edge roughness on wet and dry etched reticles manufactured at the same mask shop. These measurements were taken on a Leica LWM250, and compare identical features on both masks. A 30% improvement in line edge quality was seen on the dry etched plates. Data supporting these results is presented.