The hybrid optical proximity correction (OPC) verification flow uses both compact and rigorous lithography
models. This is the approach we are investigating to meet the challenges to improve the accuracy while keeping the
turnaround time (TAT) in check for each new technology node.
The compact lithography model is derived from the Hopkins method to calculate the image at the wafer. They
consist of the pre-calculated optical kernel set that includes properties of projection, source optics, and the resist
effects. The image at the wafer is formed by the convolution of optical kernel set with the mask transmission. The
compact model is used for OPC and lithography rule checking (LRC) due to its excellent TAT in full chip
applications. Leading edge technology nodes, however, are inherently more sensitive to process variation and
typically contain more low contrast areas, sometimes resulting in marginal hotspots. In these localized areas, it is
desirable to have access to more predictive first principle lithography simulation. The Abbe method for lithography
simulation includes full 3D resist models which solve from the first principles (the reaction/diffusion equation of the
post exposure bake) to provide the highest accuracy. These rigorous models have the ability to provide added
insight into the 3D developed profile in resist at the wafer level to assist in the application of OPC, verification and
disposition of hotspots found by LRC using compact models.
The hybrid OPC verification takes the advantage of compact model for TAT and rigorous model for 3D profile
accuracy , . And since the rigorous lithography simulator already supports new technologies like double pattern
technology (DPT), electron beam (E-beam)  and extreme ultraviolet lithography (EUV)  this approach is
extendable to multiple technology nodes.
As semiconductor technologies move toward 70nm
generation and below, contact-hole is one of the most
challenging features to print on wafer. There are two
principle difficulties in defining small contact-hole
patterns on wafer. One is insufficient process margin
besides poor resolution compared with line-space pattern.
The other is that contact-hole should be made through
pitches and random contact-hole pattern should be
fabricated from time to time.
PIXBAR technology is the candidate which can help
improve the process margin for random contact-holes.
The PIXBAR technology lithography attempts to
synthesize the input mask which leads to the desired
output wafer pattern by inverting the forward model from
mask to wafer. This paper will use the pixel-based mask
representation, a continuous function formulation, and
gradient-based interactive optimization techniques to
solve the problem. The result of PIXBAR method helps
gain improvement in process window with a short
learning cycle in contact-hole pattern assist-feature
The fast pattern shrinkage of DRAM has driven the lithography technology into the low k1 regime for sub-60 nm technology node. There are a lot of resolution enhancement techniques (RETs) e.g. OPC (Optical Proximity Correction), SB (Scattering Bar), SRAF (Sub-Resolution Assist Features) and DDL (Double Dipole Lithography) and Alternating PSM to enable the low k1 lithography . However, among the RETs, the alternating PSM technique is a high cost solution because double exposure is needed to avoid phase conflict error. Therefore, the implementation of alternating PSM with single exposure for gate conductor layer is the main purpose of this study. Many kinds of pattern and phase designs in the main cell and periphery were investigated.
Each new technology node tests the limits of optical lithography. As exposure wavelength is reduced, new imaging techniques are needed to maximize resolution capabilities. The phase shift mask (PSM) is one such technique that is utilized to push the limits of optical lithography. Altering the optical phase of the light that transmits through a photo mask can increase the resolution of a lithographic image significantly. There are several types of phase shift mask and each has a general charateristic in which some transparent area of the mask are given 180° shift in optical phase relative to other nearby transparent areas. The interaction of the aerial images between two features with a relative phase difference of 180° create interference regions that can be used to printed images much closer together and with an increased depth of focus than that of a standard chrome-on-glass mask. An AAPSM is fabricated using a subtractive process in which the quartz substrate is etched to a given depth to produce the desired phase shift. However, intensity imbalances between the etched and non-etched regions due to sidewall scattering can cause resolution, phase and placement errors on the wafer. One method to balance the transmission is 40 nm undercut with 16 nm shifter width bias. Based on our previous study, 40 nm undercut with 16 nm shifter width bias showed an improved balance of intensities between the etched and non-etched regions. The object of this experiment is to implement the AAPSM with 40 nm undercut and 16 nm shifter width bias in SRAM product and the exposure wavelength is 193 nm. The main purpose is to proof the technology of AAPSM with 40 nm undercut and 16 nm shifter width bias in real product. Also verifying all issue of AAPSM in production. In this study, the image imbalance has been corrected via 40 nm undercut and 16 nm shifter width bias, and the DOF of AAPSM for wafer print performance is larger than binary mask. The DOF of AAPSM is about 0.5 μm and the conventional binary mask is 0.3μm.