The fast pattern shrinkage of DRAM has driven the lithography technology into the low k1 regime for sub-60 nm technology node. There are a lot of resolution enhancement techniques (RETs) e.g. OPC (Optical Proximity Correction), SB (Scattering Bar), SRAF (Sub-Resolution Assist Features) and DDL (Double Dipole Lithography) and Alternating PSM to enable the low k1 lithography . However, among the RETs, the alternating PSM technique is a high cost solution because double exposure is needed to avoid phase conflict error. Therefore, the implementation of alternating PSM with single exposure for gate conductor layer is the main purpose of this study. Many kinds of pattern and phase designs in the main cell and periphery were investigated.
CPL technology is one of the powerful methods for Resolution Enhancement Technology. With high NA and strong off-axis illumination CPL has a very high resolution and is capable of printing complex 2D patterns. Image using off-axis illumination with an attenuated phase shift mask can also improve process latitude. We can combine two technologies in one mask with same off-axis illumination condition to have more flexible application. Normally CPL technology is applied in binary mask and Qz is etched for 180 degree phase. To fulfill this hybrid mask we can apply Qz etch in current normal attenuate PSM blank and E-Beam 2nd writing is also can be applied for the zebra structure. To form the different application in different area we use 5 times writing in this hybrid mask process. Also the Qz etching process is very important because the Qz etching is strongly related to the Cr-Mosi-Qz three layer profile. So a L9 DOE has been applied for Qz etching parameter fine tuning. We will optimize the phase uniformity, phase linearity, profile, CD linearity and CD proximity through the DOE.