The introduction of finFET has contributed tremendously in making scaling beyond 20nm a reality. However, the complexity of these 3D high performance transistors generate inherent new defects that are difficult to detect and this heightens concerns over device quality and reliability at future technology nodes. New methods and approaches are thus needed to effectively detect and monitor this new class of defects. Color imaging in Scanning Electron Microscopy (SEM) is not a new phenomenon. However, its use in inline SEM based defect review in the semiconductor industry is relatively new. In this work SEM color imaging is used to enhance SEM review redetection of a buried defect, Gate to Source/Drain short in 14nm finFET device. Defect sites on the wafer are flagged as defect events by Bright Field (BF) defect inspection tools. The review tool uses SEM optics to redetect the defect event using a combination of very high electron landing energies in excess of 5 keV and high beam current of about 3,000 pA to confirm the existence of the defect. The defect signal is further processed through a color coder by the SEM review equipment to create a “false” color image to enhance defect redetection and help to accurately classify defect.
This paper summarizes the work completed to determine if and how an electron beam affects the performance, reliability, and yield of an advanced copper semiconductor device. This study was done in the Kilby Fab of Texas Instruments located in Dallas, Texas. As IC technologies advance to smaller and smaller dimensions, the techniques used to detect defects needs to advance as well. Also the unique nature of defects and the defect mechanisms for copper dual damascene processes are much different than what was seen in the past with Al technologies that further complicate defect detection. The days of using only visible light to inspect wafers for defects is coming to an end. For these advanced technology devices, killer defects can be smaller than 0.15mm in size and may be invisible optically. To detect these types of defects, new light sources must be used to be able resolve these. Scanning electron beam (SEM) inspection has been introduced recently as a new tool to detect these defects and to give further capability to detect defects that may only have an electrical signature. For the defects which exhibit electrical defect characteristics, the scanning electron beam inspection tool can be used to charge the device under the scan causing a voltage contrast and actually detect electrical abnormalities in the circuit that can be caused by a defect in some underlying area. There has been much concern in the semiconductor industry however; that the electron beam itself can damage or affect the transistor characteristics due to the high voltage, or landing energy that is commonly used in an electron beam system. The depth of penetration of the electron beam into the layer of the wafer is dependent on the energy of the electron beam striking the surface. Another concern is that through time, the chamber walls are deposited with various contaminants such as carbon due to outgassing and the interaction of the electron beam and certain materials on the surface of the wafer being inspected, this material can be left on the surface of the wafer where the electron beam scanned. This residue can then affect the processing subsequent to the electron beam inspection causing adhesion issues or improper deposition. This paper will detail a study in which an advanced technology copper dual damascene logic device, along with a defect density test device, are subject to a scanning electron beam inspection at numerous points in the process and attempt to document the effects on the transistor performance and wafer processing. The results that were obtained from both sets of tests were that neither the transistor parametrics nor reliability were affected by the electron beam.