Litho-etch-litho-etch (LELE) double patterning lithography (DPL) is a strong candidate for BEOL patterning at the 20nm
logic half-node (sub-80nm pitch). In double patterning lithography, layout pattern features must be assigned opposite
colors if their spacing is less than the minimum coloring spacing. However, complex layouts usually have features that
are separated by less than the minimum coloring spacing for any coloring assignment. To resolve the minimum coloring
spacing constraint, a pattern feature (polygon) can be split into two different-color segments, introducing a stitch at the
splitting location. Although many DPL layout decomposition heuristics have been proposed, the impact of stitches on
circuit performance is not clearly analyzed. In this work, we study the impact of stitches on BEOL electrical performance
based on analytical RC equations. Our studies with 45nm (commercial) and 22nm (ITRS) technology parameters show
that (1) optimal stitching location can reduce delay variation by 5%, and (2) introducing redundant stitches (i.e., splitting
an interconnect segment intentionally) can potentially reduce circuit delay variation.
We provide new yield-aware mask strategies to mitigate emerging variability and defectivity challenges. To address variability, we analyze critical dimension variability with respect to reticle size and its impact on parametric yield. With a cost model that incorporates mask, wafer, and processing cost, considering throughput, yield, and manufacturing volume, we assess various reticle strategies (e.g., single-layer reticle, multiple-layer reticle, and small and large size) considering field-size-dependent parametric yield. To address defectivity, we compare parametric yield due to extreme ultraviolet mask blank defects for various reticle strategies in conjunction with reticle floorplan optimizations such as shifting of the mask pattern within a mask blank to avoid defects being superposed by performance-critical patterns of a design.
In this paper, we provide new yield-aware mask strategies to mitigate emerging variability and defectivity challenges. To
address variability, we analyze CD variability with respect to reticle size, and its impact on parametric yield. With a cost
model that incorporates mask, wafer, and processing cost considering throughput, yield, and manufacturing volume, we
assess various reticle strategies (e.g., single layer reticle (SLR), multiple layer reticle (MLR), and small and large size)
considering field-size dependent parametric yield. To address defectivity, we compare parametric yield due to EUV mask
blank defects for various reticle strategies in conjunction with reticle floorplan optimizations such as shifting of the mask
pattern within a mask blank to avoid defects being superposed by performance-critical patterns of a design.
Techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits
are described. These results are from multi-discipline, collaborative university-industry research and emphasize
anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes
design and testing electronic monitors in silicon at 45 nm and
fast-CAD tools to identify systematic variations for entire
chip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppress
random variability components. The Design-for-Manufacturing research includes double pattern decomposition in the
presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and
speed, the extension of timing analysis methodology to capture across process-window effects and electrical processwindow
Line-end pullback is a major source of patterning problems in low-k1 lithography. Lithographers have been well-served by geometric metrics such as critical dimension (CD) at a gate edge; however, the ever-rising contribution of line-end extension to layout area necessitates reduced pessimism in qualification of line-end patterning. Electrically aware metrics for line-end extension can be helpful in this regard. The device threshold voltage is, with nominal patterning, a weak function of line-end shapes. However, the electrical impact of line-end shapes can increase with overlay errors, since displaced line-end extensions can be enclosed in the transistor channel, and nonideal line-end shape will manifest as an additional gate CD variation. We propose a super-ellipse parameterization that enables exploration of a large variety of line-end shapes. Based on a gate capacitance model that includes the fringe capacitance due to the line-end extension, we model line-end-dependent incremental current Ion and Ioff to reflect inverse narrow width effect. Last, we calculate the Ion and Ioff considering line-end shapes as well as line-end extension length, and we define a new electrical metric for line-end extension-namely, the expected change in Ion or Ioff under a given overlay error distribution. Our model accuracy is within 0.47% and 1.28% for Ion and Ioff, respectively, compared to 3-D TCAD simulation in a typical 45-nm process. Using our proposed electrical metric, we are able to quantify the electrical impact of optical proximity correction, lithography, and design rule parameters, and we can quantify trade-offs between cost and electrical characteristics.
We present Interference Assisted Lithography (IAL) as a promising and cost-effective solution for extending lithography. IAL achieves a final pattern by combining an interference exposure with a trim exposure. The implementation of IAL requires that today's 2D random layouts be converted to highly regular 1D gridded designs. We show that an IAL-friendly 6T SRAM bitcell can be designed following 1D gridded design rules and that the electrical characteristics is comparable to today's 2D design. Lithography simulations confirm that the proposed bitcell can be successfully imaged with IAL.
As optical lithography advances into the 45nm technology node and beyond, new manufacturing-aware design requirements
have emerged. We address layout design for interference-assisted lithography (IAL), a double exposure method that
combines maskless interference lithography (IL) and projection lithography (PL); cf. hybrid optical maskless lithography
(HOMA) in  and . Since IL can generate dense but regular pitch patterns, a key challenge to deployment of IAL is
the conversion of existing designs to regular-linewidth, regular-pitch layouts. In this paper, we propose new 1-D regular
pitch SRAM bitcell layouts which are amenable to IAL. We evaluate the feasibility of our bitcell designs via lithography
simulations and circuit simulations, and confirm that the proposed bitcells can be successfully printed by IAL and that
their electrical characteristics are comparable to those of existing bitcells.
A major source of patterning problems in low-k1 lithography is line-end pullback. Though geometric metrics such as CD
at gate edge have served as good indicators, the ever-rising contribution of line-end extension to layout area necessitates
reducing pessimism in qualifying line-end patterning. Electrically-aware metrics for line-ends can be helpful in this
regard. In this work, we calculate the Ion and Ioff impact of line-end taper shapes as well as line-end length. The proposed
models are verified using TCAD simulation in a typical 65nm process. We observe that the device threshold voltage is a
weak function of line-end pullback, and that the electrical impact of the taper can vary with overlay errors. We apply a
non-uniform channel length model in addition to the proposed taper-dependent threshold voltage model to calculate ΔIon
and ΔIoff. Finally, the electrical metric for line-end printing is defined as expected change in Ion or Ioff under a given
overlay error distribution. We also propose a super-ellipse form to parameterize taper shapes, and then explore a large
variety of taper shapes to characterize electrical impact.