Inverse lithography technology (ILT) has become one of the key technologies in recent years for highly optimized mask synthesis of physical layout of large scale semiconductor designs. Localized printability enhancement (LPE) has also proved useful in applying computational lithography to repair so-called hotspots to efficiently refine the designs for better process windows without re-optimizing the entire design. Although such a localized design refinement on a relatively small number of hotspots is already quite useful, in reality, it is possible that there are a large number of hotspots, thereby necessitating handling of large volume data in the repair flow. In the case of memory designs, in particular, the number of hotspots in highly repetitive patterns can be enormous, if they are counted from the flattened layout point of view. Since hotspots on repetitive patterns tend to involve processing of repeated patterns, applying pattern matching techniques becomes a natural solution such that only one instance of the repeated patterns is fully re-optimized and its result is copied and pasted over the remaining instances of the same pattern. It is also important to take advantage of the design hierarchy, because flattening of layers in repetitive hierarchical designs can result in data volume expansion that is so massive that even trivial operations such as copying and Boolean operations could become prohibitively slow. We present techniques to exploit pattern matching as well as hierarchical processing to achieve a high performance distributed hotspots reoptimization flow.
In this paper we study the trade-offs and benefits of using ILT-based SRAF placement/OPC over conventional SRAF placement/OPC for various front-end and back-end design configurations on a full chip. We explore the use models and benefits of using ILT-based Local Printability Enhancement (LPE) in an automated flow to eliminate hot spots that can be present on the full chip after conventional SRAF placement/OPC. We study the impact on process-window, performance, and mask manufacturability.
This paper extends the state of the art by describing the practical material’s challenges, as well as approaches to minimize their impact in the manufacture of contact/via layers using a grapho-epitaxy directed self assembly (DSA) process. Three full designs have been analyzed from the point of view of layout constructs. A construct is an atomic and repetitive section of the layout which can be analyzed in isolation. Results indicate that DSA’s main benefit is its ability to be resilient to the shape of the guiding pattern across process window. The results suggest that directed self assembly can still be guaranteed even with high distortion of the guiding patterns when the guiding patterns have been designed properly for the target process. Focusing on a 14nm process based on 193i lithography, we present evidence of the need of DSA compliance methods and mask synthesis tools which consider pattern dependencies of adjacent structures a few microns away. Finally, an outlook as to the guidelines and challenges to DSA copolymer mixtures and process are discussed highlighting the benefits of mixtures of homo polymer and diblock copolymer to reduce the number of defects of arbitrarily placed hole configurations.
Inverse lithography technology (ILT) is a procedure that optimizes the mask layout to produce an image at the wafer with the targeted aerial image. For an illumination condition optimized for dense pitches, ILT inserts model-based subresolution assist features (AF) to improve the imaging of isolated features. ILT is ideal for random contact hole patterns, in which the AF are not at intuitive locations. The raw output of ILT consists of very complex smooth shapes that must be simplified for an acceptable mask write time. It is challenging for ILT to quickly converge to the ideal pattern as well as to simplify the pattern to one that can be manufactured quickly. ILT has many parameters that effect process latitude, background suppression, conversion run time, and mask write time. In this work, an optimization procedure is introduced to find the best tradeoff between image quality and run time or write time. A conversion run time reduction of 4.7× is realized with the outcome of this optimization procedure. Simulations of mask write time quantify the ability of ILT to be used for full chip applications. The optimization procedure is also applied to alternate mask technologies to reveal their advantages over commonly used 6% attenuated phase shift masks.
Sub-resolution assist features (SRAF) insertion using mask synthesis process based on pixel-based mask
optimization schemes has been studied in recent years for various lithographical schemes, including 6%
attenuated PSM (AttPSM) with off-axis illumination. This paper presents results of application of the pixelbased
optimization technology to 6% and 30% AttPSM mask synthesis. We examine imaging properties of
mask error enhancement factor (MEEF), critical dimension (CD) uniformity, and side-lobe printing for
random contact hole patterns. We also discuss practical techniques for manipulating raw complex shapes
generated by the pixel-based optimization engine that ensure mask manufacturability.
SRAF insertion through inverse microlithography methodologies has been explored at length in recent
years as one of the most promising approaches to determining the right placements of Model-based SRAF
(MBSRAF) for complex two dimensional geometrical configurations for advanced nodes. This work will
discuss the latest development of MBSRAF insertion software at Mentor Graphics. The software system
operates on the principles of inverse methods of microlithography or pixel inversion. The ability to
examine the image of every pixel in the work region as well as the mathematical solution to synthesize the
mask shapes as a cost minimization problem make it possible to reliably deal with SRAF insertion for
advanced illumination schemes such as quasar, dipole and cross-quad. Pixel inversion involving high
transmission attenuated PSM as well as hard PSM will be also discussed. We will also report on the MRC
capability to make the pixel inversion mask shapes manufacturable.
The imaging of Contact Hole (CH) layouts is one of the most challenging tasks in hyper-NA lithography. Contact Hole
layouts can be printed using different illumination conditions, but an illumination condition that provides good imaging
at dense pitches (such as Quasar or Quadrupole illumination), will usually suffer from poor image contrast and Depth of
Focus (DOF) towards the more isolated pitches. Assist Features (AF) can be used to improve the imaging of more
isolated contact holes, but for a random CH layout, an AF placement rule would have to be developed for every CH
configuration in the design. This makes optimal AF placement an almost impossible task for random layouts when using
rule-based AF placement. We have used an inverse lithography technique by Mentor Graphics, to treat a random contact
hole layout (drawn at minimal pitch 115nm) for imaging at NA 1.35. The combination of the dense 115nm pitch and
available NA of 1.35 makes the use of Quasar illumination necessary, and the treatment of the clip with inverse
lithography automatically generated optimal (model-based) AF for all geometries in the design. Because the inverse
lithography solution consists of smooth shapes rather than rectangles, mask manufacturability becomes a concern. The
algorithm allows simplification of the smooth shapes into rectangles and greatly improves mask write time. Wafer prints
of clips treated with inverse lithography at NA 1.35 confirm the benefit of the assist features.
Sub-resolution assist features (SRAFs) or scatter bars (SBs) have steadily proliferated through IC
manufacturer data preparation flows as k<sub>1</sub> is pushed lower with each technology node. The use of this
technology is quite common for gate layer at 130 nm and below, with increasingly complex geometric rules
being utilized to govern the placement of SBs in proximity to target layer features. Recently, model based
approaches for placement of SBs has arisen. In this work, the variety of rule-based and model-based SB
options are explored for the gate layer by using new characterization and optimization functions available
in the latest generation of correction and OPC verification tools. These include the ability to quantify
across chip CD control with statistics on a per gate basis. The analysis includes the effects of defocus,
exposure, and misalignment, and it is shown that significant improvements to CD control through the full
manufacturing variability window can be realized.
Inverse microlithography solves problem of finding the best mask to print target layout. We present theoretical analysis
of objective functions and algorithms that are used for inversion. We analyze complexity, speed and limitations of the
Sub-resolution assist feature (SRAF) is widely used to improve lithographic performance. Rule-based SRAF insertion has been working well for one dimensional cases but becomes quite complex for 2-dimensional arbitrary layout. In addition, the best rule generation involves a large amount of simulation and empirical data collection. Therefore model-based SRAF insertion is much more desirable especially for 65nm node and below. In this work we use the newly developed pixel inversion method for a true model-based SRAF insertion. We'll extend our work from contact layer to lines and spaces layer to demonstrate the capability of this method for all critical layers of 65nm node. This method will be used in combination with model-based OPC to achieve the required overlapping process window and CD control. Furthermore, the manufacture issues such as mask making time and mask inspection will be examined and reported.
Optical Proximity Correction (OPC) has become an indispensable tool used in deep sub-wavelength lithographic processes. OPC has been quite successful at reducing the linewidth dispersion across a product die, and also improving the overlapping process window of all printed features. This is achieved solely by biasing the mask features such that all print on target at the same dose. Recent advances in process window modeling, combined with highly customizable simulation and correction engines, have enabled process-aware OPC corrections. Building on these advances, the authors will describe a fast Process Window OPC (PWOPC) technique. This technique results in layouts with reduced sensitivity to defocus variations, less susceptibility to bridging and pinching failures, and greater coverage of over/underlying features (such as contact coverage by metal).