KEYWORDS: Time division multiplexing, Telecommunications, Multiplexers, CMOS technology, Convolution, System on a chip, Computer programming, Multiplexing, Integrated circuits, Data communications
The programmable Time Division multiplexing high Viterbi decoder IP core is studied in this paper. According to
the characteristics of multiple communication system, the method of programmable time-division multiplexing is puts
forward, the high-performance and less resource occupy IP core is designed. Based on SMIC 0.18um CMOS technology,
the ASIC of IP core is test. The test results show that the IP core areas, power and frequency could satisfy demand of
real-time communication.
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