As the EUV lithography is extending beyond 7nm technology, design to mask strategy becomes more complex. New challenges including advanced OPC and ILT in mask optimization, curvilinear masks, shrinking Mask Rule Checking (MRC), Sub-Resolution Assist Features (SRAF) generation and formation, and other complex mask geometries drive the needs to study this synergy from different stages of the flow from Optical Proximity Correction (OPC), Mask Process Correction (MPC), fracturing, to mask writing and inspection. In this study, different OPC and SRAF mask formations including curvilinear masks, controlled Manhattanized approximations of curvilinear masks, and conventional masks are generated. We illustrate whether curvilinear masks have any demonstrable lithographic benefits. A quantitative comparison of how the Manhattanization impacts mask formation. The image quality metrics such as Image Log Slope (ILS), Process Viability (PV) Band, and Depth of Focus (DOF) from various OPC mask flavors including different MRC settings and different mask forms are compared and discussed. The mask manufacturability study is conducted to identify any major challenges and approaches to minimize, including assessing the value and need for native curvilinear write tool support on a MultiBeam Mask Writer (MBMW) or a single beam Vector Shaped Beam (VSB) mask writer.
The next-generation beyond 7-nm node potentially requires the implementation of subresolution assist features (SRAF) with extreme ultraviolet (EUV) lithography. This paper aims at providing a clear SRAF strategy for the next-generation beyond 7-nm node designs through a series of experiments. Various factors are considered, including stochastic effects, three-dimensional (3-D) mask effects, through-slit effects, aberrations, and pixelated source mask optimization (SMO) sources. We consider process variability bands with a variety of process conditions, including focus/dose/mask bias changes and also the normalized image log-slope/image log-slope as our objective functions, to determine what the best SRAF solution is for a set of test patterns. Inverse lithography technology is implemented to optimize both the main feature (MF) mask and SRAF placement, in particular, asymmetric SRAF placement to balance the 3-D mask effects. SRAF can potentially mitigate image shift through-focus, i.e., nontelecentricity, caused by EUV 3-D shadowing effect. This shadowing effect is pattern-dependent and contributes to the overlay variation. As we approach the next-generation beyond 7-nm node, this image shift can be more significant relative to the overlay budget, hence, we further investigate the impact of SRAF placement to the image shift. Moreover, the center of focus shift due to the large 3-D mask absorber thickness can be potentially mitigated by SRAF implementation. The common process window is significantly impacted by both the center of focus shift and the individual depth of focus and is evaluated using both metal and contact layer test cases. We study the source impact to SRAF insertion by experimenting with both a symmetric source (standard source) and an asymmetric source (SMO source). Finally, we understand the importance of using full flare map and full through-slit model (including aberration variation through-slit) in the MF correction. Furthermore, we evaluate the need of using full models in SRAF insertion. This is a necessary step to determine the strategy of SRAF implementation for the next-generation beyond 7-nm node.
The next generation beyond 7nm node potentially requires the implementation of Sub-Resolution Assist Features (SRAF) with EUV lithography. This paper aims at providing a clear SRAF strategy for the next generation beyond 7nm node designs through a series of experiments. Various factors are considered, including: stochastic effects, 3D mask effects, through-slit effects, aberrations, and pixelated SMO sources. <p> </p>EUV has 13.5nm as its wavelength, which is much smaller than the wavelength used in ArF lithography, and this gives very different imaging challenges compared to the ArF case. Due to the small wavelength and numerical aperture (NA) of the current EUV tools, depth of focus is not as significant of a concern as in DUV. Instead, EUV lithography is severely challenged by stochastic effects, which are directly linked to the slope of the intensity curve. DUV SRAF has been shown to be a powerful tool for improving NILS/ILS, as well as DOF, and here we explore how that translates into EUV imaging. In this paper, we consider Process Variability (PV) Bands with a variety of process conditions including focus/dose/mask bias changes and also the NILS/ILS as our objective functions, to determine what the best SRAF solution is for a set of test patterns. We have full investigations on both symmetric SRAF and asymmetric SRAF. <p> </p>SRAF can potentially mitigate image shift through focus, i.e. non-telecentricity, caused by EUV 3D shadowing effect. This shadowing effect is pattern dependent and contributes to the overlay variation. As we approach the next generation beyond 7nm node, this image shift can be more significant relative to the overlay budget, hence we further investigate the impact of SRAF placement to the image shift. Moreover, the Center of Focus shift due to the large 3D mask absorber thickness can be potentially mitigated by SRAF implementation. The common process window is significantly impacted by both the center of focus shift and the individual depth of focus. We study the change by adding SRAF using both a symmetric source (standard source) and an asymmetric source (SMO source). Once SRAF is inserted for the test patterns, the common process window is plotted to compare the solutions with and without SRAF. <p> </p>Finally, we understand the importance of using full flare map and full through slit model (including aberration variation through slit) in the main feature correction, but in this paper, we will further evaluate the need of using full models in SRAF insertion. This is a necessary step to determine the strategy of SRAF implementation for the next generation beyond 7nm node.
Design rules are created considering a wafer fail mechanism with the relevant design levels under various design cases, and the values are set to cover the worst scenario. Because of the simplification and generalization, design rule hinders, rather than helps, dense device scaling. As an example, SRAM designs always need extensive ground rule waivers. Furthermore, dense design also often involves "design arc", a collection of design rules, the sum of which equals critical pitch defined by technology. In design arc, a single rule change can lead to chain reaction of other rule violations. In this talk we present a methodology using Layout Based Monte-Carlo Simulation (LBMCS) with integrated multiple ground rule checks. We apply this methodology on SRAM word line contact, and the result is a layout that has balanced wafer fail risks based on Process Assumptions (PAs). This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533
In this work, we investigate the Negative Tone Develop (NTD) process from a fundamental
materials/process interaction perspective. Several key differences exist between a negative tone develop
process and a traditional positive tone develop system. For example, the organic solvent dissolves the
unexposed material, while the deprotected resist remains intact. This causes key differences in key
patterning properties, such as pattern collapse, adhesion, remaining resist, and photoresist etch selectivity.
We have carried out fundamental studies to understand these new interactions between developer and
remaining resist with negative tone develop systems. We have characterized the dynamic dissolution
behavior of a model system with a quartz crystal microbalance with both positive and negative tone solvent
developers. We have also compared contrast curves, and a fundamental model of image collapse. In
addition, we present first results on Optical Proximity Correction (OPC) modeling results of current
Negative Tone Develop (NTD) resist/developer systems.
In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography
has been explored and documented in the literature.<sup>1-5</sup> It has been shown that intensive optimization of the fundamental
degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the
source, which leads to improved lithographic performance. These efforts have driven the need for improved controllability
in illumination<sup>5-7</sup> and have pushed the required optimization performance of mask design.<sup>8, 9 </sup>This paper will present recent
experimental evidence of the performance advantage gained by intensive optimization, and enabling technologies like pixelated
illumination. Controllable pixelated illumination opens up new regimes in control of proximity effects,<sup>1, 6, 7</sup> and we
will show corresponding examples of improved through-pitch performance in 22nm Resolution Enhancement Technique
(RET). Simulation results will back-up the experimental results and detail the ability of SMO to drive exposure-count reduction,
as well as a reduction in process variation due to critical factors such as Line Edge Roughness (LER), Mask Error
Enhancement Factor (MEEF), and the Electromagnetic Field (EMF) effect. The benefits of running intensive optimization
with both source and mask variables jointly has been previously discussed.<sup>1-3</sup> This paper will build on these results by
demonstrating large-scale jointly-optimized source/mask solutions and their impact on design-rule enumerated designs.
The topography effect of Opaque MoSi on Glass (OMOG) mask on 32nm contact hole patterning is analyzed by
examining the difference of image intensity profile between thin mask approximation and rigorous electro-magnetic
field (EMF) simulation. The study shows that OMOG topography results in more than a 20% decrease of image intensity.
The impact of OMOG mask topography on lithography modeling of a 32nm contact hole process is explored by fitting
lithography simulation with experimental results for both thin mask model and EMF model. This study shows that thin
mask modeling is a good approximation of EMF modeling for a contact pitch larger than 120nm, but yields about 10nm
prediction error for a 110nm contact pitch. Thin mask modeling is shown to be inaccurate in predicting critical
dimension of contact arrays with sub-resolution assistant feature (SRAF). In addition, thin mask modeling is too
pessimistic in predicting SRAF printability. In contrast, EMF model shows good prediction of contact arrays with and
without sub-resolution feature. A modified thin mask modeling technique utilizing an effective SRAF size is proposed
and verified with experimental results.
Historically, lithographic scaling was driven by both improvements in wavelength and numerical aperture. Recently,
the semiconductor industry completed the transition to 1.35NA immersion lithography. The industry
is now focusing on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh
diffraction. Here, the IBM Alliance demonstrates the extendibility of several double patterning solutions that
enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through
innovative processes. This paper details a set of solutions that have enabled early 22 nm learning through careful
The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA
immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical
challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning
technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development
alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling
the pattern spatially through mask design or temporally through innovative processes. These techniques have been
successfully employed for early 32nm node development using 45nm generation tooling. Four different double
patterning techniques were implemented. The first process illustrates local RET optimization through the use of a
split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging
properties and the illumination conditions for each are independently optimized. These regions are then printed
separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that
could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging
with particular focus on both line-end dimension and linewidth control . A double exposure-double etch (DE2)
approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process,
optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that
the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures
with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole
lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay
tolerant . Collectively, the double patterning solutions developed for early learning activities at 32nm can be
extended to 22nm applications.
Birefringence, polarization, and wavelength filtering properties of subwavelength transmission gratings (SWTGs) and their applications in vertical cavity surface emitting lasers (VCSELs) are presented. Particularly, large birefringence (over two orders of magnitude larger than natural birefringence crystals) and polarization effects have been achieved in thin (240 nm thick or less) amorphous silicon subwavelength gratings (SWTGs). The SWTG polarizers were used to control the polarization of VCSELs (i.e., fixing, enhancing and switching of the polarization), making the maximum polarization of a VCSEL creased to 300:1 from 20:1. The SWTG's waveplates were used to build a polarization-switching VCSEL oscillator that has a can tunable frequency up to terahertz.