Optical overlay metrology has been used for years as the baseline for overlay control, measuring an optical target in the scribe line with optimized design to best match the on-product overlay. However, matching the optical target overlay measurements to the real on-product overlay becomes a serious challenge for most advanced technology nodes and forces the industry to develop different or complementary solutions. To identify and better quantify the different, well-known overlay accuracy detractors, in this work we have used optical and state-of-the-art electron beam technologies (eBeam) to measure on-product and on-optical target overlay errors of a wafer processed at imec using 5 nm technology node design rules and intentionally introduced overlay skews of +10 and -10 nm in x and y axis. The overlay errors as measured by the SEM eBeam system, equipped with elluminator™ technology which enables fast see through measurements of overlay which has been compared with (X-sectional) STEM-HAADF reference overlay metrology data. The on-product and optical target SEM overlay measurements show very similar wafer maps, in line with the applied overlay errors during the lithography exposure step. eBeam and TEM data show excellent correlation for the on-product overlay errors and the eBeam data also reveal a significant bias of ~ 6 nm between on-product and on-target overlay errors. From these results it can be concluded that manufacturing of advanced devices which require accurate OPO control, will need new metrology strategies that combine eBeam and optical or, eventually, use only eBeam technologies to guarantee effective overlay control with sufficient accuracy.
Metrology of most advanced CMOS devices poses more and more challenges: lithography and etch patterning processes need to be controlled on critical parameters that -beyond critical dimensions (CD)- nowadays also include line width and line edge roughness (LWR/LER), multiple patterning induced pitch-walk and, due to the high aspect ratio of the patterned structures, also thermo-mechanical structural bending.
In this paper, it is shown that sufficient sampling is required to ensure that scanning transmission electron microscopy (STEM) does provide relevant information about the dimensions and chemical composition of the advanced devices. While, in principle, STEM can measure device dimensions with Angstrom resolution and sub-nm precision, a single measurement will not be representative for the device dimensions that are known to vary statistically (LER/LWR) as well as systematically (Pitch-walk, structural bending).
In this context, the metrology capabilities of a (calibrated) automated 80-200kV STEM with Cs aberration corrector and a high efficiency EDS detector have been evaluated for both STEM-EDS and STEM-HAADF acquisitions. It will be shown that, when measuring multiple (~ 400) individual FinFET structures (Silicon Fins / dummy Silicon gate lines), average CD, LER and LWR can be quantified from the distribution of measured line widths and line pitches, that SADP and SAQP induced pitch-walk may show up as multi-modal pitch distributions, and that pitch walking can be quantified if also structural bending, that is observed, is properly taken into account.
Finally, the STEM and EDS metrology capabilities for FinFET and NanoWire (NW) device structures are reviewed for different use cases (statistical process control and technology development support) and with different indicators (Precision over Tolerance ratio (P/T) and Variability ratio (r = 1 – σ2metrology / σ2measured process )).
The scaling of device dimensions has resulted in a need for high resolution metrology techniques capable of measuring small CDs with a high degree of precision and accuracy. Scanning transmission electron microscopy (STEM) has previously been demonstrated to be a metrology technique capable of measuring small CDs and gathering large volumes of accurate and precise metrology data. In addition, energy dispersive X-ray spectroscopy (EDS) metrology has also been demonstrated to be a powerful technique enabling the detection and measurement of low contrast layers, specifically for 3D NAND devices. Benchmarking EDS metrology against STEM metrology in terms of precision and accuracy is important to further investigate the capabilities of EDS metrology for the semiconductor industry. This study was performed using the latest technology in EDS detectors, along with automated acquisition and metrology software to generate large metrology data sets on horizontal nanowire structures. In this paper, we present data to support our finding that EDS metrology is well-matched with STEM metrology in terms of both precision and accuracy. In addition, we discuss the capability of EDS and STEM metrology to detect subtle process variations in next-generation logic devices.
Monitoring of pattern roughness for advanced technology nodes is crucial as this roughness can adversely affect device yield and degrade device performance. The main industry work horse for in-line roughness measurements is the CD-SEM, however, today no adequate reference metrology tools exist that allow to evaluate its roughness measurement sensitivity and precision. To bridge this gap, in this work the roughness measurement capabilities of different analytical techniques are investigated. Different metrology methods are used to evaluate roughness on a same set of samples and results are compared and used in a holistic approach to better characterize and quantify the measured pattern roughness. To facilitate the correlation between the various metrology techniques and the evaluation of CD-SEM sensitivity, an effective approach is to induce pattern roughness in a controlled way by adding well defined levels of roughness to the designed patterns on a EUV mask and to measure the response and sensitivity of CD-SEM and of the other techniques to these different pattern roughness levels once printed on wafers. This paper presents the roughness measurement results obtained with various metrology technologies including CD-SEM, OCD, S-TEM and XCD on EUV Lithography patterned wafers both postlithography and post-etch. The benefits of recently developed metrology enhancements are demonstrated as well; automated TEM allows to generate accurate and rather precise reference roughness data, Machine Learning enables OCD based roughness metrology with good correlation to CD-SEM and STEM, and the improved sensitivity of EUV and X-ray scattering systems allows to extract roughness information that does correlate to CD-SEM.
We aim at resolving deca-nanometer features in microelectronic samples using a laboratory SEM-based X-ray tomography
microscope. Such a system produces X-rays through the interaction between a focused SEM electron beam and a metallic
target. The effective source size of the X-ray beam can be adjusted by varying the target material and geometry. For
instance, the use of tungsten nanowires (few hundred nanometers of length) combined with a high electron beam current
leads to an increased X-ray flux generated in a reduced volume, necessary for detecting interface details of the analyzed
object. It improves resolution and signal-to-noise ratio (SNR), but is also sensitive to electron beam-target instabilities
during the scan. To improve robustness, a FFT-based image correlation is integrated in the process through a closed-loop
control scheme. It allows stabilizing the electron beam on the target and to preserve the X-ray flux intensity and alignment.
Also, a state of the art high-resolution scientific-CMOS (sCMOS) X-ray detector was installed, allowing to reduce noise
and to increase quantum efficiency. Results show that such numerical and equipment improvements lead to significant
gains in spatial resolution, SNR and scanning time of the SEM-based tomography. It paves the way to routine, high
resolution, 3D X-ray imaging in the laboratory.
Full wafer dual beam FIB-SEM systems have received a lot of industrial interest in the last years and by now are operational in several 200mm and 300mm fabs. These tools offer a 3D-physical characterization capability of defects and device structures and as such allow for more rapid yield learning and increased process control. Moreover, if SEM resolution is insufficient to reveal defect origin or the necessary process details, it is now also possible to prepare TEM samples using a controlled, easy to learn in-situ process and to efficiently continue the characterization with a high resolution TEM inspection. Thanks to latest hardware developments and the high degree of automation of this TEM sample preparation process, wafers no longer need to be broken and remain essentially free from contamination. Hence, the TEM lamella process can be considered as non-destructive and wafers may continue the fabrication process flow.
In this paper we examine the SEM and TEM application capabilities offered by in-line dual beam systems. To qualify the wafer return strategy, the particle contamination generated by the system hardware as well as the process-induced contamination have been investigated. The particle levels measured are fully acceptable to adopt the wafer return strategy. Ga-contamination does exist but is sufficiently low and localized so that the wafer return strategy can be applied safely in the back-end of line process. Yield analysis has confirmed that there is no measurable impact on device yield. Although yet to be proven for the frond-end of line processes, the wafer return strategy has been demonstrated as a valuable one already in the backend of line processes. The as developed non-destructive 3-D SEM-TEM characterization capability does offer value added data that allow to determine the root cause of critical process defects in almost real-time and this for both standard (SEM) and more advanced (TEM) technologies.
In an industrial environment, new techniques based on the surface photovoltage measurement (SCA and SPV), are shown to detect sodium, aluminum, iron contamination in the range of E + 10/cm2. Variations in the measurements due to wafer samples or oxidation recipe are determined. From these results, a procedure for preparing monitoring samples is established. It is demonstrated that these monitoring tools are useful to monitor equipment but a correlation between the defectivity on a 12 nm gate oxide and SCA and SPV results with the same recipes was not obtained.