For mature technology nodes, main yield detractor is random defectivity.
Nevertheless, some devices can show higher defectivity than rest of devices. Out of
process accident, design related defect is one of suspected root cause. Also, design-based
defect category is expected to increase as technology node decreases. Determining origin
of these additional systematic defects is not easy as these defects are usually residual for
technologies in production, not always predictable by OPC simulator (ex: void defect in
active STI structure), and at least hidden by random defectivity after in-line wafer
In this paper, an automatic flow to track systematic defects within global
defectivity is presented. This flow starts with a relevant selection of several inspection
defect files for a given device. Then the Design Based Binning (DBB) tool performs a
fine alignment of the whole multi wafer inspection data set with design file. The resulting
aligned defect file is treated by an efficient pattern matching algorithm to generate a
design-based binning (DBB) defect file. The integration of this output defect file into a
Yield Management System (YMS) allows easy defect analysis and statistical correlation to electrical results. An example of design-based defects tracking analysis and their impact on yield of a mature technology node device is presented in this paper.
It is a well established fact that as design rules and printed features shrink, sophisticated
techniques are required to ensure the design intent is indeed printed on the wafer. Techniques of this
kind are Optical Proximity Correction (OPC), Resolution Enhancement Techniques (RET) and DFM
Design for Manufacturing (DFM). As these methods are applied to the overall chip and rely on
complex modeling and simulations, they increase the risk of creating local areas or layouts with a
limiting process window. Hence, it is necessary to verify the manufacturability (sufficient depth of
focus) of the overall die and not only of a pre-defined set of metrology structures. The verification
process is commonly based on full chip defect density inspection of a Focus Exposure Matrix (FEM)
wafer, combined with appropriate post processing of the inspection data. This is necessary to avoid
time consuming search for the Defects of Interest (DOI's) as defect counts are usually too high to be
handled by manual SEM review. One way to post process defect density data is the so called design
based binning (DBB). The Litho Qualification Monitor (LQM) system allows to classify and also to
bin defects based on design information. In this paper we will present an efficient way to combine
classification and binning in order to check design rules and to determine the marginal features
(layout with low depth of focus).
The Design Based Binning has been connected to the Yield Management System (YMS) to allow
new process monitoring approaches towards Design Based SPC. This could dramatically cut the
time to detect systematic defects inline.
It is well known that as design rule shrink advanced techniques are required in-order to precisely and controllably print
the design intent on a wafer. The commonly used techniques to overcome the resolution limit are OPC and RET. The
goal of these techniques is to compensate for an expected local interaction between the light, mask pattern and photoresist,
which will otherwise result in a mismatch between the printed pattern and design intent and lead to fatal yield
failures. It is this interaction which dominates the extensive time-consuming mask qualification fabs are required to
perform before a new mask on a new product can be inserted into a production line.
In this paper, a new approach and Litho Qualification Monitor (LQM) system, implemented in Qimonda Dresden fab,
for ultra fast pattern failure classification based on design information (Design Based Binning), coupled with an
automatic interface to SEM metrology tool will be presented. The system centralizes all the operations required for the
identification and analysis of marginally-printed systematic structures.