The thin nature of EUV (Extreme Ultraviolet) resist has posed significant challenges for etch processes. In particular, EUV patterning combined with conventional etch approaches suffers from loss of pattern fidelity in the form of line breaks. A typical conventional etch approach prevents the etch process from having sufficient resist margin to control the trench CD (Critical Dimension), minimize the LWR (Line Width Roughness), LER (Line Edge Roughness) and reduce the T2T (Tip-to-Tip). Pre-etch deposition increases the resist budget by adding additional material to the resist layer, thus enabling the etch process to explore a wider set of process parameters to achieve better pattern fidelity. Preliminary tests with pre-etch deposition resulted in blocked isolated trenches. In order to mitigate these effects, a cyclic deposition and etch technique is proposed. With optimization of deposition and etch cycle time as well as total number of cycles, it is possible to open the underlying layers with a beneficial over etch and simultaneously keep the isolated trenches open. This study compares the impact of no pre-etch deposition, one time deposition and cyclic deposition/etch techniques on 4 aspects: resist budget, isolated trench open, LWR/LER and T2T.
Although lens aberrations in EUV imaging systems are very small, aberration impacts on pattern placement error and overlay error need to be carefully investigated to obtain the most robust lithography process for high volume manufacturing. Instead of focusing entirely on pattern placement errors in the context of a single lithographic process, we holistically study the interaction between two sequential lithographic layers affected by evolving aberration wavefronts, calculate aberration induced overlay error, and explore new strategies to improve overlay.
Pellicles that satisfy transmission, emission, thermal, and mechanical requirements are highly desired for EUV high volume manufacturing. We present here the capability of integrating pellicles in the full flow of rigorous EUV lithography simulations. This platform allows us to investigate new coherence effects in EUV lithography when pellicle is used. Critical dimension uniformity and throughput loss due to pellicle defects and add-on particles are also analyzed. Our study provides theoretical insights into pellicle development and facilitates pellicle insertion in EUV lithography.
The layout design for silicon photonics can be complicated and usually have edges with arbitrary angles. The critical dimension can be less than 100 nm, requiring the layouts to be OPCed in order to have large enough process windows for high volume manufacturing. However, the well-established CMOS-orientated IC industry OPC tools for advanced nodes can only handle Manhattan designs in which the Manhattan style polygons with edges of 0°, 90° or 45° to the reference direction. Silicon photonics layouts need to be discretized in order to use the existing OPC tools. From optical performance point of view, the design grid is expected to be as small as possible and it is usually from 1 nm to 5 nm. However, the design grid has never been optimized based on the OPC performance.
In this paper, we demonstrate the impacts of design grid on the OPC performance. Design grid for silicon photonics is not always the smaller the better anymore. Our study shows that small 2D designs require large design grids while smooth curves with large radius require small design grids.
We proposed a novel design-based discretization algorithm to convert a non-Manhattan style layout to an OPC-friendly Manhattan style layout. Simulation results show that the pattern fidelity is optimized for both small 2D patterns and smooth curves.
Stochastic-induced roughness of lithographic features continues to be of great concern due to its impact on semiconductor devices. In particular, rare events (large deviations in edge positions due to roughness) can cause catastrophic failure of a chip, but are hard to predict. Here, a new methodology, the level crossing method, is used to characterize the statistical behavior of edge roughness with the goal of predicting extreme events. Using experimental results from EUV lithography, the distribution of edge deviations was found to have tails significantly heavier than a normal distribution. While further work is required, these heavy tails could prove problematic when EUV is used in high volume manufacturing.
Optical metrology tool, LX530, is designed for high throughput and dense sampling metrology in semiconductor manufacture. It can inspect the dose and focus variation in the process control based on the critical dimension (CD) and line edge roughness (LER) measurement. The working principle is shown with a finite-difference-time-domain (FDTD) CD simulation. Two optical post lithography wafers, including one focus-exposure-matrix (FEM) wafer and one nominal wafer, are inspected for CD, dose and focus analysis. It is demonstrated that dose and focus can be measured independently. A data output method based on global CD uniformity (CDU), inter CDU and intra CDU is proposed to avoid the data volume issue in dense sampling whole wafer inspection.
Unlike optical masks which are transmissive optical elements, use of extreme ultraviolet (EUV) radiation requires a reflective mask structure - a multi-layer coating consisting of alternating layers of high-Z (wave impedance) and low-Z materials that provide enhanced reflectivity over a narrow wavelength band peaked at the Bragg wavelength.1 Absorber side wall angle, corner rounding,<sup>2</sup> surface roughness,<sup>3</sup> and defects<sup>4</sup> affect mask performance, but even seemingly simple parameters like bulk reflectivity on mirror and absorber surfaces can have a profound influence on imaging. For instance, using inaccurate reflectivity values at small and large incident angles would diminish the benefits of source mask co-optimization (SMO) and result in larger than expected pattern shifts.<p> </p> The goal of our work is to calculate the variation in mask reflectivity due to various sources of inaccuracies using Monte Carlo simulations. Such calculation is necessary as small changes in the thickness and optical properties of the high-Z and low-Z materials can cause substantial variations in reflectivity. This is further complicated by undesirable intermixing between the two materials used to create the reflector.<sup>5</sup> One of the key contributors to mask reflectivity fluctuation is identified to be the intermixing layer thickness. We also investigate the impacts on OPC when the wrong mask information is provided, and evaluate the deterioration of overlapping process window. For a hypothetical N7 via layer, the lack of accurate mask information costs 25% of the depth of focus at 5% exposure latitude. Our work would allow the determination of major contributors to mask reflectivity variation, drive experimental efforts of measuring such contributors, provide strategies to optimize mask reflectivity, and quantize the OPC errors due to imperfect mask modeling.
The shrink in feature sizes enabled by EUV lithography introduces a regime where stochastic limits to resolution can manifest in the form of line edge roughness (LER) for line/space patterns and local critical dimension uniformity (LCDU) for contact/holes. To meet increasing tolerances on edge placement error (EPE) and suppression of stochastic effects, an understanding of EUV mask contributions on lithographic patterning variability is essential. The work here explores stochastic noise originating from the mask patterning process and attempts to quantify its contributions towards on-wafer LCDU. A semiempirical approach was used to statistically decompose the mask variability component from the measured LCDU and provide a first-order understanding of the mask’s impact on wafer. Taking a more direct approach, a one-to-one correlation of local CD variation between mask and wafer was also experimentally shown, presenting the possibility for predicting the contributions and impact of mask LCDU on wafer prior to exposure.
Our paper will use stochastic simulations to explore how EUV pattern roughness can cause device failure through rare events, so-called "black swans". We examine the impact of stochastic noise on the yield of simple wiring patterns with 36nm pitch, corresponding to 7nm node logic, using a local Critical Dimension (CD)-based fail criteria Contact hole failures are examined in a similar way. For our nominal EUV process, local CD uniformity variation and local Pattern Placement Error variation was observed, but no pattern failures were seen in the modest (few thousand) number of features simulated. We degraded the image quality by incorporating Moving Standard Deviation (MSD) blurring to degrade the Image Log-Slope (ILS), and were able to find conditions where pattern failures were observed. We determined the Line Width Roughness (LWR) value as a function of the ILS. By use of an artificial "step function" image degraded by various MSD blur, we were able to extend the LWR vs ILS curve into regimes that might be available for future EUV imagery. As we decreased the image quality, we observed LWR grow and also began to see pattern failures. For high image quality, we saw CD distributions that were symmetrical and close to Gaussian in shape. Lower image quality caused CD distributions that were asymmetric, with "fat tails" on the low CD side (under-exposed) which were associated with pattern failures. Similar non-Gaussian CD distributions were associated with image conditions that caused missing contact holes, i.e. CD=0.
Initial readiness of EUV (extreme ultraviolet) patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. With the substantial cost of EUV exposure there is significant interest in extending the capability to do single exposure patterning with EUV. To enable this, emphasis must be placed on the aspect ratios, adhesion, defectivity reduction, etch selectivity, and imaging control of the whole patterning process. Innovations in resist materials and processes must be included to realize the full entitlement of EUV lithography at 0.33NA. In addition, enhancements in the patterning process to enable good defectivity, lithographic process window, and post etch pattern fidelity are also required. Through this work, the fundamental material challenges in driving down the effective k1 factor will be highlighted.
Lithographic patterning at the 7 and 5 nm nodes will likely require EUV (λ=13.5 nm) lithography for many of the critical
levels. All optical elements in an EUV scanner are reflective which requires the EUV photomask to be illuminated at an
angle to its normal. Current scanners have an incidence of 6 degree, but future designs will be <6 degrees for high-NA
systems. Non-telecentricity has been shown to cause H-V bias due to shadowing, pattern shift through focus, and image
contrast lost due to apodization by the reflective mask coating. A thinner EUV absorber can dramatically reduce these
issues. Ni offers better EUV absorption than Ta-based materials, which hold promise as a thinner absorber candidate.
Unfortunately, the challenge of etching Ni has prevented its adoption into manufacturing. We propose a new absorber
material that infuses Ni nanoparticles into the TaN host medium, allowing for the use of established Ta etching chemistry.
A thinner is absorber is created due to the enhanced absorption properties of the Ni-Ta nano-composite material. Finite
integral method and effective medium theory-based transfer matrix method have been independently developed to analyze
the performance of the nano-composite absorption layer. We show that inserting 15% volume fraction Ni nanoparticles
into 40-nm of TaN absorber material can reduce the reflection below 2% over the EUV range. Numerical simulations
confirm that the reduced reflectivity is due to the increased absorption of Ni, while scattering only contributes to
approximately 0.2% of the reduction in reflectivity.
Critical back end of line (BEOL) Mx patterning at 7nm technology node and beyond requires sub-36nm pitch line/space pattern in order to meet the scaling requirements. This small pitch can be achieved by either extreme ultraviolet (EUV) lithography or 193nm-immersion-lithography based self-aligned quadruple patterning (SAQP). With enormous challenges being faced in production readiness of EUV lithography, SAQP is expected to be the front up approach for Mx grid patterning for most of industry. In contrast to the front end of line (FEOL) fin patterning, which has successfully deployed SAQP approach since 10nm node technology, BEOL Mx SAQP is challenging owing to the required usage of significantly lower temperature budgets for film stack deposition. This has an adverse impact on the material properties of the as-deposited films leading to emergence of several challenges for etch including selectivity, uniformity and roughness.
In this presentation we will highlight those unique etch challenges associated with our BEOL Mx SAQP patterning strategy and summarize our efforts in optimizing the patterning stack, etch chemistries & process steps for meeting the 7nm technology node targets. We will present comparison data on both organic and in-organic mandrel stacks with respect to LER/LWR & CDU. With LER being one of the most critical targets for 7nm BEOL Mx, we will outline our actions for optimization of our stack including resist material, mandrel material, spacer material and others. Finally, we would like to update our progress on achieving the target LER of 1.5 nm for 32nm pitch BEOL SAQP pattern.
EUV based patterning is one of the frontrunner candidates enabling scaling for future technology nodes. However it poses the common challenges of ‘pattern roughness’ and ‘etch resistance’ aspect which are getting even more critical as we work on smaller dimension features. Continuous efforts are ongoing to improve resist materials and lithography process but the industry is slowly moving to introduce it at high volume manufacturing. Plasma Etch processes have the potential to improvise upon the incoming pattern roughness and provide improved LER/LWR downstream to expedite EUV progress. In this work we demonstrate the specific role of passivation control in the dualfrequency Capacitively Coupled Plasma (CCP) for EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for line/space patterns. We draw the implicit commonalities between different passivation chemistry and their effectiveness for roughness improvement. The effect of relative C:F and C:H ratio in feed gas on CFx and CHx plasma species and in turn the evolution of pattern roughness is drawn. Data that shows the role of plasma etch parameters impacting the key patterning metrics of CD, resist selectivity and LER/LWR is presented.
The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.
The left side and right side line edge roughnesses (LER) of a line are compared for different conditions, such as through pitch, through critical dimension (CD), from horizontal to vertical line direction, from litho to etch. The investigation shows that the left and right side LER from lithography process are the same, however, the metrology can cause a 4-25% increase in the measured right side LER. The LER difference is related to the CDSEM e-beam scan direction.
The line edge roughness (LER) and line width roughness (LWR) transfer in a self-aligned quadruple patterning (SAQP) process is shown for the first time. Three LER characterization methods, including conventional standard deviation method, power spectral density (PSD) method and frequency domain 3-sigma method, are used in the analysis. The wiggling is also quantitatively characterized for each SAQP step with a wiggling factor. This work will benefit both process optimization and process monitoring.
Line edge roughness (LER) and line width roughness (LWR) are analyzed based on the frequency domain 3σ LER characterization methodology during pattern transfer in a self-aligned double patterning (SADP) process. The power spectrum of the LER/LWR is divided into three regions: low frequency, middle frequency, and high frequency regions. Three standard deviation numbers are used to characterize the LER/LWR in the three frequency regions. Pattern wiggling is also detected quantitatively during LER/LWR transfer in the SADP process.
A frequency domain 3 sigma LER characterization methodology combining the standard deviation and power spectral density (PSD) methods is proposed. In the new method, the standard deviation is calculated in the frequency domain instead of the spatial domain as in the conventional method. The power spectrum of the LER is divided into three regions: low frequency (LF), middle frequency (MF) and high frequency (HF) regions. The frequency region definition is based on process visual comparisons. Three standard deviation numbers are used to characterize the LER in the three frequency regions. Pattern wiggling can be detected quantitatively with a wiggling factor which is also proposed in this paper.
The successful demonstration of 637 wafer exposures in 24 hours on the EUV scanner at the IBM EUV Center for
Excellence in July marked the transition from research to process development using EUV lithography. Early process
development on a new tool involves significant characterization, as it is necessary to benchmark tool performance and
process capability. This work highlights some key learning from early EUV process development with a focus on
identifying the largest sources of variability for trench and via hole patterning through the patterning process. The EUV
scanner demonstrated stable overlay on a 40 lot test run using integrated wafers. The within field and local critical
dimension uniformity (CDU) are the largest contributors to CD variations. The line edge roughness (LER) and line
width roughness (LWR) in EUV resist will be compared to the post etch value to determine the effect of processing.
While these numbers are generally used to describe the robustness of 1D trenches or circular vias, the need to accurately
evaluate the printability of irregular 2D features has become increasingly important. In the past 5 years, models built
from critical dimension scanning electron microscope (CDSEM) contours has become a hot topic in computational
lithography. Applying this methodology, the CDSEM contour technique will be used to assess the uniformity of these
irregular patterns in EUV resist and after etching. CDSEM contours also have additional benefits for via pattern
In EUV lithography, the short wavelength of the light makes the topography of the mask stand out as three dimensional objects rather than thin masks. This generally requires use of a rigorous scattering simulator to calculate the diffracted orders of a mask in order to explain experimental results. In contrast, for optical proximity correction we cannot afford such detailed calculations and we would like to replace such detailed simulations with faster methods that give similar results. In this paper, we discuss observations we made during our printing experiments on a 0.33 NA EUV projection system. In order to extend the process window for non-nested trenches we introduced clear assist features. We observed strong tilt of Bossung curves and best focus shifts for certain pitches. These shifts can be explained by a phase difference between main and assist feature. This effect is very similar for both horizontal and vertical trenches, and it depends strongly on the illumination of the mask. We find that the best focus shift can be minimized for certain assist pitches and illumination conditions, but a general solution for random pitches
appears not obvious.
The overlay performance and alignment strategy optimization for a triple patterning (LELELE) were studied based on the Monte Carlo simulation method. The simulated results show that all of the combined or worst case overlay, alignment strategy, mean target of the upper level, and mean tolerance of the lower level are dependent on the means of the lower level. A dynamic mean control method is proposed to be integrated into the APC system to improve the overlay performance.
The most decent scanning electron microscopy (SEM) can provide image magnification up to 500kX which seems to be suitable to image semiconductor devices for the advanced technology nodes. However, SEM images at such a high magnification often suffer from the drift and space related displacement errors, potentially causing image blur and distortion. To circumvent this, we apply the super-resolution (SR) technique to enhance the resolution of the CD-SEM metrology by using the advanced signal processing algorithms. The resolution enhancement can be realized by exploiting the multiple low resolution (LR) images that include unique information of an imaging target by looking at a slightly different position. We experimentally demonstrate image quality improvement gained by the SR technique after correcting the time-dependent drift/displacement and mapping estimated information onto the high resolution (HR) pixel grid with the non-linear pixel interpolation scheme. In addition, estimating the time-dependent drifts of the wafer position could be useful to investigate the drift properties of the CD-SEM tool.
Flare (stray light) is an important effect impacting extreme ultraviolet lithography (EUVL) imaging system performance. Four flare measurement methods including Kirk, modulation transfer function, double exposure, and zonal ring approximation method are reviewed and analyzed theoretically. The point spread function of an EUV NXE:3100 exposure tool is extracted from the measured Kirk flare (KF) and fitted with a double-fractal model. The KF for this NXE:3100 tool is determined to be 8.5% for a 2-μm diameter absorber pad placed in a 12-mm outer radius bright field, which is larger than the previous 5% KF data measured by ASML and IMEC in 2011. The observation of the increased flare level in the NXE:3100 tool suggests that contamination of EUV optics may be a potential problem for EUVL manufacturing.
Extreme ultraviolet lithography (EUVL) at 13.5 nm is currently the most promising technology for advanced integrated circuit manufacturing nodes. Since the wavelength for EUVL is an order of magnitude smaller than current optical lithography systems (193 nm), aberration tolerances on lens manufacturing must be tightened to avoid image distortion and contrast loss as they scale with wavelength. Therefore, understanding the aberrations of an EUVL system both in idle and production conditions is paramount. This study aims to assess a photoresist-based aberration metrology technique for capturing pupil information of EUVL systems that can be implemented during full system use. Several datasets have been collected on a full-field EUVL system. Various one-dimensional and two-dimensional binary structures were imaged and used for pupil wave front extraction in conjunction with computational modeling and simulations. Results show a successful extraction of a stable aberration signature over several measurements, showing the method to be sensitive to subnanometer levels of intentional aberration change through lens manipulation.
With numerical apertures > 0.4 there will be broad ranges of angles of incidence of light on masks for EUV systems with 4× lens reduction, leading to several undesirable consequences with current MoSi multilayers and tantalum-based absorbers. An option for reducing the range of incident angles is to increase the lens reduction, but this entails small field sizes with standard 6" mask form factors or necessitates the use of larger masks sizes. Small fields lead to a need for stitching or accepting substantially reduced throughput - a problem for a technology already challenged with respect to cost-of-ownership. The implementation of larger mask formats is straightforward but requires considerable investments in new tools for mask making. New absorbers may provide a solution for high-NA EUV lithography at 4× lens reduction, but much R&D is required to demonstrate that this approach will work.
Both 90.9° and 180° phase shifts have been achieved using a new Phase Shift Mask (PSM) structure. This PSM is intended for use as a focus monitor. Both the EUV images of the focus monitor patterns on the new EUV PSM test mask, obtained from the SEMATECH/Berkeley Actinic Inspection Microscope (AIT), and the SEMATECH EUV Micro
Exposure Tool (MET), shows that an alternating PSM EUV mask can be effectively used for EUVL focus monitoring.
Extreme Ultraviolet Lithography (EUVL) at 13.5 nm is currently the most promising technology for advanced integrated circuit (IC) manufacturing nodes. Since the wavelength for EUVL is an order of magnitude smaller than current optical lithography systems (193 nm), wavelength scaled tolerances on lens manufacturing must be tightened to avoid image distortion and contrast loss as these scale with wavelength. Therefore understanding the aberrations of an EUVL system both in idle and production conditions is paramount. This study aims to assess a photoresist based technique for capturing pupil information of EUVL systems that can be implemented during full system use. Several data sets have been collected on an ASML EUV Alpha-Demo Tool (ADT) using the latest Center for Nanoscale Science and Engineering (CNSE) baseline resist Shin-Etsu SEVR139. Various one-dimensional and two-dimensional binary structures were imaged and used for pupil extraction in conjunction with computational modeling and simulations. Results show a stable extracted aberration signature over several measurements. Results also show that the method is sensitive to sub-nm levels of aberration change.
Although the k1 factor is large for extreme ultraviolet (EUV) lithography compared to deep ultraviolet (DUV)
lithography, OPC is still needed to print the intended patterns on the wafer. This is primarily because of new
non-idealities, related to the inability of materials to absorb, reflect, or refract light well at 13.5nm, which must
be corrected by OPC. So, for EUV, OPC is much more than conventional optical proximity correction. This work
will focus on EUV OPC error sources in the context of an EUV OPC specific error budget for future technology
nodes. The three error sources considered in this paper are flare, horizontal and vertical print differences, and
mask writing errors. The OPC flow and computation requirements of EUV OPC are analyzed as well and
compared to DUV. Conventional optical proximity correction is simpler and faster for EUV compared to DUV
because of the larger k1 factor. But, flare and H-V biasing make exploitation of design hierarchy more difficult.
The first use of extreme ultraviolet (EUV) lithography in logic manufacturing is targeted for the 14 nm node, with
possible earlier application to 20-nm node logic device back-end layers to demonstrate the technology. Use of EUV
lithography to pattern the via-levels will allow the use of dark-field EUV masks with low pattern densities and will
postpone the day when completely defect-free EUV mask blanks are needed. The quality of the imaging at the 14 nm
node with EUV lithography is considerably higher than with double-dipole or double-exposure double-etch 193-nm
immersion lithography, particularly for 2-dimensional patterns such as vias, because the Rayleigh k<sub>1</sub>-value when printing
with 0.25 numerical aperture (NA) EUV lithography is so much higher than with 1.35 NA 193-nm immersion
lithography and the process windows with EUV lithography are huge. In this paper, the status of EUV lithography
technology as seen from an end-user perspective is summarized and the current values of the most important metrics for
each of the critical elements of the technology are compared to the values needed for the insertion of EUVL into
production at the 14 nm technology node.