Cross-talk characterization results of high-fill-factor single-photon avalanche diode (SPAD) arrays in CMOS 150-nm technology are reported and discussed. Three different SPAD structures were designed with two different sizes (15.6 and 25.6 μm pitch) and three guard ring widths (0.6, 1.1, and 1.6 μm). Each SPAD was implemented in an array, composed of 25 (5×5) devices, which can be separately activated. Measurement results show that the average cross-talk probability is well below 1% for the shallow-junction SPAD structure with 15.6 μm pitch and 39.9% fill factor, and 1.45% for the structure with 25.6 μm pitch and 60.6% fill factor. An increase of cross-talk probability with the excess bias voltage is observed.
The characterization of two Single-Photon Avalanche Diodes (SPADs) structures fabricated in CMOS 150nm technology is reported in this paper. The structures are based on a pwell/n-iso junction and differ only for the presence of a polysilicon layer above the guard ring. Each structure is implemented in two different shapes (circular and square) and four sizes (5,10,15 and 20μm). Measurement results show that both average breakdown voltage and non-uniformity decrease with SPAD sizes. The statistical variation of Photon Detection Efficiency (PDE) and its dependence on device size are also reported and discussed. For all the considered device sizes, a PDE non-uniformity lower than 0.5% was measured.
The SPADnet FP7 European project is aimed at a new generation of fully digital, scalable and networked photonic components to enable large area image sensors, with primary target gamma-ray and coincidence detection in (Time-of- Flight) Positron Emission Tomography (PET). SPADnet relies on standard CMOS technology, therefore allowing for MRI compatibility. SPADnet innovates in several areas of PET systems, from optical coupling to single-photon sensor architectures, from intelligent ring networks to reconstruction algorithms. It is built around a natively digital, intelligent SPAD (Single-Photon Avalanche Diode)-based sensor device which comprises an array of 8×16 pixels, each composed of 4 mini-SiPMs with in situ time-to-digital conversion, a multi-ring network to filter, carry, and process data produced by the sensors at 2Gbps, and a 130nm CMOS process enabling mass-production of photonic modules that are optically interfaced to scintillator crystals. A few tens of sensor devices are tightly abutted on a single PCB to form a so-called sensor tile, thanks to TSV (Through Silicon Via) connections to their backside (replacing conventional wire bonding). The sensor tile is in turn interfaced to an FPGA-based PCB on its back. The resulting photonic module acts as an autonomous sensing and computing unit, individually detecting gamma photons as well as thermal and Compton events. It determines in real time basic information for each scintillation event, such as exact time of arrival, position and energy, and communicates it to its peers in the field of view. Coincidence detection does therefore occur directly in the ring itself, in a differed and distributed manner to ensure scalability. The selected true coincidence events are then collected by a snooper module, from which they are transferred to an external reconstruction computer using Gigabit Ethernet.
There have been many reports of application-specific or custom designed high dynamic range (HDR) CMOS
image sensors. To achieve their extended dynamic range, these sensors utilize techniques that can
significantly degrade their signal-to-noise ratios (SNR). We utilize a simplified sensor model to compare two
HDR techniques with a conventional APS sensor regarding their SNR and dynamic range (DR). We perform a
new analysis of a mixed APS and time-to-saturation sensor that shows that it can detect similar high
illuminations levels that the multiple capture sensor without degrading the SNR at lower levels. Furthermore,
the time-to-saturation sensor can be adjusted on-the-fly to detect specific illumination levels with optimized