In this paper we review two motion detection models based on
insect's visual system. The two motion detection models are the
Horridge template model and the Reichardt correlator model, both have
been implemented in analog VLSI. We briefly review the VLSI
implementation of the two motion detection models and identify the difficulties in designing the required large RC time constants in
VLSI. Possible circuit designs to obtain RC time constants in the order of 10-100 ms are presented.
In this paper a new low power area efficient serial-to-parallel shift register design is presented. The design of the register only contains 4 transistors per stage and uses a capacitive bootstrapping technique to offset the threshold voltage drop of MOSFETs. We shall refer to this logic family as Non-Ratioed Bootstrap Logic (NRBL). The intended target applications are in smart sensor arrays and image sensors for use in the select registers to control the photo diode array.