The steady march of Moore's law demands ever smaller feature sizes to be printed and
Optical Proximity Correction to correct to ever tighter dimensional tolerances. Recently
pitch doubling techniques has relieved the pressure on CD reduction, which instead of
being achieved lithographically are reduced by subsequent etching or chemical
interaction with spin-on layers. CD tolerance reductions, however, still need to match the
overall design rule shrinkage. The move to immersion lithography, where effective
Numerical Apertures now reach 1.35, has been accompanied by a significantly reduction
in depth of focus, especially on isolated contacts. To remedy this, RET techniques such
as assist feature placement, have been implemented. Certain local placements of assist
features and neighboring contacts are observed to result in highly elliptical contacts being
printed. In some layouts small changes in the aspect ratio of the contact on the mask leads
to strong changes in the aspect ratio of the printed contact, whereas in other layouts the
response is very weak. This effect can be described as an aspect ratio MEEF. The latter
type of contact can pose a significant challenge to the OPC recipe which is driven by the
need to place the printed contour within a small range of distance from target points
placed on the midpoint of edges of a nominally square contact. The OPC challenge
naturally will be compounded when the target layout is rectangular in the opposite sense
to the natural elliptical shape of the printed contact. Approaches to solving this can vary
from intervening at the assist feature placement stage, at the possible loss of depth of
focus, to accepting a certain degree of ellipticity in the final contour and making the OPC
recipe concentrate on minimizing any residual errors. This paper investigates which
contact layouts are most challenging, discusses the compromises associated with
achieving the correction target and results are shown from a few different approaches to
resolving these issues.
In double-patterning technology (DPT), we study the complex interactions of layout creation, physical design and design
rule checking flows for the 22nm and 16nm device nodes. Decomposition includes the cutting (splitting) of original
design-intent features into new overlapping polygons where required; and the coloring of all the resulting polygons into
two mask layouts. We discuss the advantages of geometric distribution for polygon operations with the limited range of
influence. Further, we find that even the naturally global coloring step can be handled in a geometrically local manner.
We analyze and compare the latest methods for designing, processing and verifying DPT methods including the 22nm
and 16nm nodes.
Decomposition of an input pattern in preparation for a double patterning process is an inherently global
problem in which the influence of a local decomposition decision can be felt across an entire pattern. In
spite of this, a large portion of the work can be massively distributed. Here, we discuss the advantages
of geometric distribution for polygon operations with limited range of influence. Further, we have found
that even the naturally global "coloring" step can, in large part, be handled in a geometrically local
manner. In some practical cases, up to 70% of the work can be distributed geometrically. We also
describe the methods for partitioning the problem into local pieces and present scaling data up to 100
CPUs. These techniques reduce DPT decomposition runtime by orders of magnitude.
In this paper we study interactions of double patterning technology (DPT) with lithography, optical proximity correction (OPC) and physical design flows for the 22-nm device node. DPT methods decompose the original design intent into two individual masking layers, which are each patterned using single exposures and existing 193-nm lithography tools. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step that will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons, where required, and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals, such as reduce circuit area, minimize relayout effort, ensure DPT compliance, guarantee patterning robustness on individual layer targets, ensure symmetric wafer results, and create uniform wafer density for the individual patterning layers.
Double patterning technology (DPT) is one of the main options for printing critical layers at
32nm half-pitch and beyond. To enable DPT, a layout decomposition tool is first used to split the
original design into two separate decomposed-design layouts. Each decomposed-design layout
may then receive optical proximity correction (OPC) and RETs to produce a mask layout. The
requirements for OPC to enable individual layer DPT patterning are generally the same as
current single exposure OPC requirements, meaning that the success criteria will be similar to
previous node specifications. However, there are several new challenges for OPC with DPT.
These include large litho-etch biases, two sets of process variables associated with each
patterning layer and the relative pattern placement between them. The order of patterning may be
important as there may be process interactions between the two patterns especially at overlap
regions. Corners which were rounded in single patterning layers may now become sharp,
potentially increasing reliability concerns due to electromigration. In this study, we address many
of these issues by proposing several new techniques that can be used in OPC with DPT. They
are specifically designed for the Litho-Etch-Litho-Etch process, but some of the ideas may be
extended to develop OPC methods for other DPT processes. We applied the new OPC method to
several circuit and test patterns and demonstrated how OPC results were improved compared to
regular OPC methods.
A challenge in model-based assist feature placement is to find optimal placements while satisfying
mask rules and preventing AF printing. There are numerous strategies for achieving this ranging
from fully rule-based methods to pixel-based inversion. Our proposed solution is to identify the
optimal locations of assist features using modeling information based strictly on optics and resist
stack optical characteristics. Once these positions have been found, preliminary AFs can be placed.
At this point suggested sizes and shapes can be identified, although these can later be modified. In a
later step, MRC cleanup, printability fixing, and main-pattern OPC can be performed simultaneously.
This has the advantage of allowing the use of the full process model to predict the location of OPC
edges accurately, and use calibrated or 3d mask models to determine assist feature printing behavior.
This correction is done while maintaining MRC constraints. In this flow, an AF placement field,
generated from the pre-OPC target patterns, can be used to provide accurate guidance on how to
move assist features to get the most benefit while keeping other constraints in mind. Using this
method, a range of printability fixing strategies, guided by placement benefits, is available. We
present data showing that the benefit of AF placements can be determined from optical parameters,
on target (non-OPC) data, and that this method leads to beneficial yet compliant masks.
Double Patterning is seen as the prime technology to keep Moore's law on path while EUV technology is
still maturing into production worthiness. As previously seen for alternating-Phase Shift Mask
technology, layout compliance of double patterning is not trivial [2,3] and blind shrinks of anything but
the most simplistic existing layouts, will not be directly suitable for double patterning. Evaluating a
production worthy double patterning engine with highly non-compliant layouts would put unrealistic
expectations on that engine and provide metrics with poor applicability for eventual large designs. The true
production use-case would be for designs that have at least some significant double patterning compliance
already enforced at the design stage. With this in mind a set of ASIC design blocks of different sizes and
complexities were created that were double patterning compliant. To achieve this, a set of standard cells
were generated, which individually and in isolation were double patterning compliant, for multiple layers
simultaneously. This was done using the automated Standard Cell creation tool Cadabra<sup>TM</sup> . To create a
full ASIC, however, additional constraints were added to make sure compliance would not be broken
across the boundaries between standard cells when placed next to each other . These standard cells were
then used to create a variety of double patterning compliant ASICs using iCCompiler<sup>TM</sup> to place the cells
correctly. Now with a compliant layout, checks were made to see if the constraints made at the micro level
really do ensure a fully compliant layout on the whole chip and if the coloring engine could cope with such
large datasets. A production worthy double patterning engine is ideally distributable over multiple
processors [6,7] so that fast turn-around time can be achievable on even the largest designs. We
demonstrate the degree of linearity of scaling achievable with our double patterning engine. These results
can be understood together with metrics such as the distribution of the sizes of networks requiring coloring
resulting from these designs.
Double patterning has gained prominence as the most likely lithographic methodology to help keep Moore's law going
towards 32nm 1/2 pitch lithography. While solutions, to date, have focused mainly on gap splitting to avoid minimum
spacing violations, the decomposition should, ideally, also attempt to optimize the process window of the decomposed
masks. A major contributor to process window sensitivity is the correct placement of sub-resolvable assist features.
These features are placed once the polygons of each mask are defined, i.e. post decomposition. If some awareness of this
downstream process step is made available to the double patterning decomposition stage, then a more robust
decomposition can be achieved.
Double patterning has gained prominence as the most likely methodology to help keep Moore's law going towards 22nm 1/2 pitch lithography. However, most designs cannot be blindly shrunk to run using only two patterning layers and a variety of constraints must be imposed on designs to allow for correct decomposition. These constraints are more onerous for the contact layer than for line/space patterns because they more easily form odd cycles on the 2D plane, which cannot be broken using polygon cutting. As this can adversely limit packing density, especially in bit cells, a triple patterning decomposition capability could be attractive for the contact layer. Pattern decomposition for contacts can be likened to coloring a map where minimum spaces between contacts are replaced with borders. It is well known that 4 colors can color any map, but it is an NP-complete problem to compute the minimum number of colors needed to color any given map. This should place an upper limit on the scalability of any algorithm able to color large networks. A variety of test patterns that are known 3-colorable are needed to compare suitable algorithms. It has been proved that a set of aperiodic tiling known as "Penrose Tiles" is 3-colorable. This paper compares the scalability of different coloring algorithms using a variety of contact patterns based on Penrose Tiles.
Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and
its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and
specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AF's print
more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present,
mask manufacturers must downsize AF's below 30nm to solve this problem. This is challenging and increases mask cost.
We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in
terms of DOF after OPC. We have devised an effective algorithm that removes printing AF's. It can not only search for
the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as
design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and
incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF
printing problems economically and accurately.
Double patterning technology (DPT) is one of the main options for printing logic devices with half-pitch
less than 45nm; and flash and DRAM memory devices with half-pitch less than 40nm. DPT methods
decompose the original design intent into two individual masking layers which are each patterned using
single exposures and existing 193nm lithography tools. The results of the individual patterning layers
combine to re-create the design intent pattern on the wafer. In this paper we study interactions of DPT with
lithography, masks synthesis and physical design flows. Double exposure and etch patterning steps create
complexity for both process and design flows. DPT decomposition is a critical software step which will be
performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of
original design intent polygons into multiple polygons where required; and coloring of the resulting
polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize
rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure
symmetric wafer results; and create uniform wafer density for the individual patterning layers.
Delays in equipment availability for both Extreme UV and High index immersion have led to a growing
interest in double patterning as a suitable solution for the 22nm logic node. Double patterning involves
decomposing a layout into two masking layers that are printed and etched separately so as to provide the
intrinsic manufacturability of a previous lithography node with the pitch reduction of a more aggressive
node. Most 2D designs cannot be blindly shrunk to run automatically on a double patterning process and so
a set of guidelines for how to layout for this type of flow is needed by designers. While certain classes of
layout can be clearly identified and avoided based on short range interactions, compliance issues can also
extend over large areas of the design and are hard to recognize. This means certain design practices should
be implemented to provide suitable breaks or performed with layout tools that are double patterning
compliance aware. The most striking set of compliance errors result in layout on one of the masks that is at
the minimum design space rather than the relaxed space intended. Another equally important class of
compliance errors is that related to marginal printability, be it poor wafer overlap and/or poor process
window (depth of focus, dose latitude, MEEF, overlay). When decomposing a layout the tool is often
presented with multiple options for where to cut the design thereby defining an area of overlap between the
different printed layers. While these overlap areas can have markedly different topologies (for instance the
overlap may occur on a straight edge or at a right angled corner), quantifying the quality of a given overlap
ensures that more robust decomposition solutions can be chosen over less robust solutions. Layouts which
cannot be decomposed or which can only be decomposed with poor manufacturability need to be
highlighted to the designer, ideally with indications on how best to resolve this issue. This paper uses an
internally developed automated double pattern decomposition tool to investigate design compliance and
describes a number of classes of non-conforming layout. Tool results then provide help to the designer to
achieve robust design compliant layout.
KEYWORDS: Optical components, Atrial fibrillation, Image processing, Image resolution, Photomasks, Optical proximity correction, System on a chip, Systems modeling, Model-based design, Process modeling
Demanding process window constraints have increased the need for effective assist feature placement algorithms that are robust and flexible. These algorithms must also allow for quick ramp up when changing nodes or illumination conditions. Placement based on the optical components of real process models has the potential to satisfy all of these requirements. We present enhancements to model-based assist feature algorithms. These enhancements include exploration of image-processing techniques that can be exploited for contact-via AF placement, model-based mask rule check (MRC) conflict resolution, the application of models to line-space patterns, and a novel placement technique for contact-via layers using a specially-built single modeling kernel.
The upcoming 45nm and 32nm device generations will continue the familiar industry lithography trends of
decreased production K1 factor, reduced focus error tolerances and increased pattern density. As previous
experience has shown, small changes in the values of lithographic K1, focus tolerance and pattern density
for the process-design space can lead to large required changes in OPC and RET solutions. Therefore,
significant improvements in utility and speed are needed for these new device generations. In this paper we
highlight significant new functionality and performance capabilities using existing Field-based OPC and
RET methods. The use of dense grid calculations in Field-based methods is shown to provide a software
platform for robust and fast implementation of new model-based RET techniques such as model-based
assist feature placement and tuning. We present the performance and capability increases for model-based
RET methods. Additionally, we have studied and present the performance of production 45nm generation
field-based OPC and RET software across several different multiple-purpose hardware platforms.
Significant improvements in runtime (for approximately the same hardware cost) are observed with new
general purpose hardware platforms and with software optimization for this hardware.
Sub-Resolution Assist Features (SRAFs) are placed into patterns to enhance the through process imaging performance of
critical features. SRAFs are typically placed using complex rules to achieve optimal configurations for a pattern.
However, as manufacturing process nodes are growing increasingly complex, the SRAF placement rules will most likely
be unable to produce optimal performance on some critical features. A primary impediment to resolving these problems
is identifying poorly performing features in an efficient manner.
A new process model form referred to as a Focus Sensitivity Model (FSM) is capable of rapidly analyzing SRAF
placement for through process pattern performance. This study will demonstrate that an FSM is capable of finding suboptimal
SRAF placements as well as missing SRAFs. In addition, the study suggests that the FSM does not need to
comprehend the entire photolithography process to analyze SRAF placement. This results in simpler models that can be
generated before a manufacturing process enters its development phase.
Sub-resolution assist features (SRAFs) are an important tool for improving through-process robustness of advanced lithographic processes. Assist features have generally been placed and adjusted according to heuristic rules. The complexity of these rules increases rapidly with shrinking features size requiring more wafer data for calibration and more effort on the part of engineers. For advanced nodes, a model-based approach may better account for the variety of two-dimensional geometries and reduce substantially the amount of user effort required for effective SRAF placement. There are many ways in which model-based methods can be used to improve the effectiveness of assist features; we investigate several here. In the investigations described here, process window models may be employed to: 1) derive optimal rules for initial AF placement in a rule-based process, 2) resolve mask rule violations in optimal ways, and 3) make post-placement corrections of mask sites with poor behavior. In addition, we discuss a method for replacing an initial rule-based assist feature placement with a model-based placement which can consider the local two-dimensional geometry.
Sub-resolution assist features are an important tool for improving process robustness for one-dimensional pattern features at advanced manufacturing process nodes. However, sub-resolution assist feature development efforts have not generally considered optimization for process robustness with two-dimensional pattern features. This generally arises both from conservatively placing SRAFs to avoid the possibility of imaging, and from a desire to simplify SRAF placement rules. By studying two-dimensional features using a manufacturing sensitivity model, one can gain insight into the capabilities of SRAFs regarding two-dimensional pattern features. These insights suggest new methodologies for shaping assist features to enhance two-dimensional feature robustness. In addition, a manufacturing sensitivity model form can be employed to optimize the placement of multiple competing SRAFs in localized two-dimensional regions. Initial studies demonstrate significant pullback reduction for two-dimensional features once SRAF placement has been optimized using the manufacturing sensitivity model form.