Block copolymer directed self-assembly (DSA) is a promising extension of optical lithography
for device fabrication akin to double-patterning. The irregular distribution of contact holes in circuit
layouts is one of the biggest challenges for DSA patterning because the self-assembly tends to form
regular patterns naturally. Although the small guiding templates are shown to guide the
self-assembly off the natural geometry by strong boundary confinement [1, 2] (Fig. 1), it is
insufficient to simply surround contact holes with guiding templates without optimizing the
placement and geometry of the guiding templates.
The use of block copolymer self-assembly for device fabrication in the semiconductor industry
has been envisioned for over a decade. Early works by the groups of Hawker, Russell, and Nealey
[1-2] have shown a high degree of dimensional control of the self-assembled features over large
areas with high degree of ordering. The exquisite dimensional control at nanometer-scale feature
sizes is one of the most attractive properties of block copolymer self-assembly. At the same time,
device and circuit fabrication for the semiconductor industry requires accurate placement of desired
features at irregular positions on the chip. The need to coax the self-assembled features into circuit
layout friendly location is a roadblock for introducing self-assembly into semiconductor
manufacturing. Directed self-assembly (DSA) and the use of topography to direct the self-assembly
(graphoepitaxy) have shown great promise in solving the placement problem [3-4]. In this paper, we
review recent progress in using block copolymer directed self-assembly for patterning sub-20 nm
contact holes for practical circuits.
In many ways, sidewall spacer double patterning has created a new paradigm for lithographic roadmaps. Instead of
using lithography as the principal process for generating device features, the role of lithography becomes to generate a
mandrel (a pre-pattern) off-of-which one will subsequently replicate patterns with various degrees of density
multiplication. Under this new paradigm, the innovativeness of various density multiplication techniques is as critical to
the scaling roadmap as the exposure tools themselves.
Sidewall spacer double patterning was the first incarnation of mandrel based patterning; adopted quickly in NAND flash
where layouts were simple and design space was focused. But today, the use of advanced automated decomposition
tools are showing spacer based patterning solutions for very complex logic designs. Future incarnations can involve the
use of laminated spacers to create quadruple patterning or by retaining the original mandrel as a method to obtain triple
patterning. Directed self-assembly is yet another emerging embodiment of mandrel based patterning, where selfseparating
polymers are registered and guided by the physical constraint of a mandrel or by chemical pre-pattern trails
formed onto the substrate.
In this summary of several bodies of work, we will review several wafer level demonstrations, all of which use various
forms of mandrel or stencil based density multiplication including sidewall spacer based double, triple and quadruple
patterning techniques for lines, SADP for via multiplication, and some directed self-assembly results all capable of
addressing 15nm technology node requirements and below. To address concerns surrounding spacer double patterning
design restrictions, we show collaboration results with an EDA partner to demonstrate SADP capability for BEOL
routing layers. To show the ultimate realization of SADP, we partner with IMEC on multiple demonstrations of
While directed self-assembly of diblock copolymers is increasingly developed in terms of process flow,
metrology and evaluation are the next crucial step in maximizing its effectiveness for integration into device design
based on directed self-assembly trends. We present a novel image processing and data analysis program, SLICE (Sub-Lithography Imaging Computation and Evaluator), whose capabilities enable a systematic, automated analysis and
characterization of directed self-assembly (SA) of block copolymers for high-density circuit integration. Key features
such as defect-free region detection and trench-to-trench comparison of SA quality illustrate the potentially significant
impact of SLICE to the process optimization and commercialization of sub-lithographic techniques.
Single FETs and CMOS inverters with 20 nm contact holes patterned using self-assembled diblock copolymer are
demonstrated in this work. Alignment of the self-assembled contact holes to the MOSFET source and drain is achieved
with a unique guiding layer and the self-assembly process is integrated with an existing CMOS process flow using
conventional tools on a full 4" wafer level. Potential application for block copolymer patterning on SRAM circuit level is
We present our work on using one level of templated self-assembly using 70:30::PS-<i>b</i>-PMMA.
Focus is on the fabrication of top-gated silicon MOSFETs and simple circuits. The potential choice
as a first demonstration is to use 70:30::PS-<i>b</i>-PMMA to define the contact holes of MOSFETs.
Contact holes make a good starting point because of both their size and repetition in view of today's
design. We have presented our work of solving half-hole problem when adopting templated selfassembly.
Results of transferring the self-assembled holes from the polymer mask to a silicon
dioxide layer by plasma etching and filling the etched holes in silicon dioxide with aspect ratio of
approximately one to three are presented. Potential integration issues for making MOSFETs will also
We present our recent work on using diblock copolymer directed self-assembly for the fabrication of silicon MOSFETs. Instead of using self-assembly to assemble the entire device, we plan to utilize self-assembly to perform one critical step of the complex MOSFET process flow in the beginning. Initial results of using PS-<i>b</i>-PMMA to define pores with hexagonal array having diameter of 20 nm for contact hole patterning will be described. Potential integration issues for making MOSFETs will also be addressed.