Reliability is an important index to ensure the application of infrared focal plane arrays (IRFPAs) in complex environment, and it becomes a major bottleneck problem of IRFPAs’ development. Because of the characteristics such as type, nature, quantity, location and distribution et al, bad pixel which contains initial bad pixel and used bad pixel has outstanding advantage for failure analysis and reliability evaluation of IRFPAs. In this paper, the structure of IRPFAs has been introduced in detail, and the damage mechanisms of used bad pixel also have been analyzed deeply. At the same time, the feasibility to study IRPFAs' damage stress, failure position, damage mechanism has been discussed all around. The research of bad pixel can be used to optimize the structure and process, meanwhile it also can improve the accuracy of bad pixel identification and replacements.
This paper describes the simulation results of a high performance readout integrated circuit (ROIC) designed for long wave infrared (LWIR) detectors, which has high dynamic range (HDR). A special architecture is used to the input unit cell to accommodate the wide scene dynamic range requirement, thus providing over a factor of 70dB dynamic range. A capacitive feedback transimpedance amplifier (CTIA) provides a low noise detector interface circuit capable of operating at low input currents and a folded cascade amplifier with a gain of 73dB is designed. A 6.4pF integration capacitor is used for supporting a wide scene dynamic range, which can store 80Me. Because of the restriction of the layout area, four unit cells will share an integration capacitor. A sample and hold capacitor is also part of the input unit cell architecture, which allows the infrared focal plane arrays (IRFPA) to be operated in full frame snapshot mode and provides the maximum integration time available. The integration time is electronically controlled by an external clock pulse. The simulation results show that the circuit works well under 5V power supply and the nonlinearity is calculated less than 0.1%. The total power dissipation is less than 150mW.
An improved CMOS readout integrated circuit (ROIC) for N-on-P very long wavelength (VLWIR) detectors is designed, which has the ability to operate with a simple background suppression. It increases the integration time and the signal-to-noise ratio (SNR) of image data. A buffered gate modulation input (BGMI) cell as input circuit provides a low input resistance, high injection efficiency, and precise biasing voltage to the photodiode. By theoretically analyzing the characteristic parameters of MOS device at low temperature, a high gain’s feedback amplifier is devised which using a differential stage to provide the inverting gain to improve linearity and to provide tight control of the detector bias. The final chip is fabricated with HHNEC 0.35um 1P4M process technology. The measurement results of the fabricated readout chip under 50K have successfully verified both readout function and performance improvement. With the 5.0V power supply, ROIC provides the output dynamic range over 2.5V. At the same time, the total power dissipation is less than 200mW, and the maximum readout speed is more than 2.5MHz.
Infrared focal plane HgCdTe device is used in the environment of complicated astrospace radiation. To achieve the instrument’s actual service life, the anti-radiation ability is needed to study in our research. The irradiation-induced invalidation mechanism of semiconductor materials is introduced in this paper, and the screening experiments' total radiation dose of American Military Standard is also investigated in our study. Through the simulation of astrospace radiation effect by γ -irradiation, the experimental procedures are proved to be rational by the analysis of the experimental data. With the domestic conditions, radiation screening procedures which meets the practical need is suggested.
In our study, we designed a 512×512 readout integrated circuit (ROIC) for N-on-P short wave infrared
(SWIR) detectors, which has the ability to operate with two capacitors for different input current levels
from very low background applications to daytime high illumination conditions. A buffered direct
injection (BDI) readout cell as input circuit provides a low input resistance, high injection efficiency,
and precise biasing voltage to the photodiode at low input currents. In order to reduce the noise of the
BDI readout cell, a high-performance single stage amplifier is devised, the gain of which reaches as
high as 50dB. The input MOSFET of the amplifier operates at sub-threshold region to keep the
photodiode at precise reverse bias and steady injection efficiency. At the same time, with the input
MOSFET at sub-threshold region, the current is smaller than at saturation region, and the power
dissipation is reduced to a low level. A sample and hold circuit is also part of the input unit cell
architecture, which allows the infrared focal plane array (IRFPA) to be operated in full frame snapshot
mode and rolling mode. To prevent the excess of total current of the ROIC, the reset time of every row
has a lag of one period compared to the previous row. The simulation results confirm these advantages.
With the 5.0V power supply, ROIC provides the output dynamic range over 2.5V, the well capacity
more than 1×106e-, and the total power dissipation less than 120mW. The final chip is fabricated with
HHNEC 0.35um 1P4M process technology, and the pixel occupies a 30um×30um area. The Testing
results are coincide with the simulations of the circuit. With the detecting current varies from 30pA to
1nA, the linearity of BDI is 99%, and it can be operated at the temperatures below 77K.