Epitaxial growth of III-V compound semiconductors on Si has attracted significant attention for many years due to the potential for monolithic integration of III-V based optoelectronic devices with Si integrated circuits. There are three major problems for GaAs monolithic epitaxy on Si, respectively the large lattice mismatch, the difference in thermal expansion coefficient, and growth of a polar material on a nonpolar substrate. Various dislocation reduction techniques have been proposed, such as graded SiGe buffer layers, thermal cycles annealing (TCA), and strained-layer superlattices (SLs) as dislocation filters. Unfortunately, these methods generally require relatively thick epitaxial layers and/or complex epitaxial process. This study relates to the heteroepitaxy of GaAs on nanopatterned Si substrates using the selective aspect ratio trapping method. The dislocations originally generated at the GaAs/Si interface are mostly isolated by the SiO<sub>2</sub> side wall. High-quality GaAs nanowires have been grown on Si(001) substrates by metal-organic chemical vapor deposition. A method of two-step epitaxy of GaAs is performed to achieve a high-quality GaAs layer with a 217 arcsec narrow FWHM of HRXRD. Material quality was confirmed by Scanning electron microscope (SEM) and transmission electron microscopy (TEM). We also simulated the distribution of the light field on the nanoscale GaAs layer surround by Ag films used the FDTD method. The light field confined well in the 250nm width GaAs nanowire which can be used in the nanolasers on Silicon as light sources.