KEYWORDS: Network security, Field programmable gate arrays, Computer security, Data storage, Data processing, Reconfigurable computing, Embedded systems, Chemical elements, Computing systems, Data archive systems
Existing security solutions in network storage environment perform poorly because cryptographic operations (encryption
and decryption) implemented in software can dramatically reduce system performance. In this paper we propose a
cryptographic hardware accelerator on dynamically reconfigurable platform for the security of high performance
network storage system. We employ a dynamic reconfigurable platform based on a FPGA to implement a PowerPCbased
embedded system, which executes cryptographic algorithms. To reduce the reconfiguration latency, we apply
prefetch scheduling. Moreover, the processing elements could be dynamically configured to support different
cryptographic algorithms according to the request received by the accelerator. In the experiment, we have implemented
AES (Rijndael) and 3DES cryptographic algorithms in the reconfigurable accelerator. Our proposed reconfigurable
cryptographic accelerator could dramatically increase the performance comparing with the traditional software-based
network storage systems.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.