A high speed comparator applied to GHz gated single photon detection technology is proposed. The comparator is based on the combination of pre-amplification and dynamic regenerative latching structures, resulting in an effective improvement in response speed. In this paper, an analysis on the transmission delay of the dynamic latch comparators is presented. The proposed circuit is implemented in 350 nm CMOS technology and occupies an active area of 0.012 mm2. The delay of the whole detection system is approximately 256ps and the discrimination level of the proposed comparator is 50mV while consuming 4.7mW at supply voltages of 3.3V. The comparator can be used in a single photon gated detection system under 1 GHz condition.
A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.
In 3D imaging application, large scale of SPAD arrays, low power consumption, compact and high accuracy quenching
circuit is necessary. In this paper we developed a simple and fast pulse sensing circuit with negligible static power
dissipation, and the afterpulsing effects are also significantly reduced by fast quenching process. The gated mode is used
and it can precisely set the turn-off time of each frame. Ensure SPAD is more reliable. Compare to other active
quenching circuits (AQC) for SPADs, the proposed circuit is ultra fast in signal pulse sensing and accurate in time
resolution with a low threshold, and it can be easily utilized in SPAD-array detectors for photon-flight-time measurement
with sub-nanosecond precision. The quenching circuit implemented by CSMC 0.5-μm CMOS technology is optimal
designed by using SPICE simulator, where an accurate SPICE model we established for InGaAs SPAD is embedded. The
simulation result shows that the proposed AQC can operate properly in all the static and transient states, and the rising
time of the sensed voltage pulse can be caught in 1ns, and its quenching time is less than 5ns. This is much suitable for
picosecond precision infrared sensing system.