Maximizing yield in a modern semiconductor fab requires proper optimization of the design (layout), process technology, and fab process tool recipes. For the past decade the prevalence of systematic defects tied to design or design-process interactions have predominated over random defect sources. Previously Resolution Enhancement Technology (RET), Design For Manufacturability (DFM), and Design-Technology Co-optimization (DTCO) techniques were the successful response to eliminating systematic yield limiting patterns. Machine learning, with its ability to find trends and make predictions based on large volumes of data, provides a unique path towards further reduction in systematic defect levels. This talk will present methods based on the use of design and process info with machine learning and computational lithography methods to identify and eliminate yield limiting patterns in the design, improve the accuracy of mask generation with etch and resist modeling and OPC, and improve the productivity and accuracy of fab defect detection and diagnostics. This paper will present methods to improve EPE control and reduce systematic hotspots through both supervised and unsupervised machine learning. Specifically we will focus on 3 areas: - identifying and yield limiting patterns in the design phase. - improving the accuracy (EPE control) of mask generation with machine learning assisted etch and resist modeling and OPC. - improving the productivity and accuracy of fab defect detection and diagnostics with machine learning.
The ever increasing pattern densities and design complexities make the tuning of optical proximity correction (OPC) recipes very challenging. One known method for tuning is genetic algorithm (GA). Previously GA has been demonstrated to fine tune OPC recipes in order to achieve better results for possible 1D and 2D geometric concerns like bridging and pinching. This method, however, did not take into account the impact of excess segmentation on downstream operations like fracturing and mask writing.
This paper introduces a general methodology to significantly reduce the number of excess edges in the OPC output, thus reducing the number of flashes generated at fracture and subsequently the write time at mask build. GA is used to reduce the degree of unwarranted segmentation while ensuring good OPC quality. An Objective Function (OF) is utilized to ensure quality convergence and process-variation (PV) plus an additional weighed factor to reduce clustered edge count.
The technique is applied to 14nm metal layer OPC recipes in order to identify excess segmentation and to produce a modified recipe that significantly reduces these segments. OPC output file sizes is shown to be reduced by 15% or more and overall edge count is shown to be reduced by 10% or more. At the same time overall quality of the OPC recipe is shown to be maintained via OPC Verification (OPCV) results.
Sub-Resolution Assist Feature (SRAF) printing detection is critical during SRAF model building. Currently, SRAF printing detection on silicon wafer is mainly through human judgement on CDSEM images, which is inefficient and error prone. Therefore, a robust automatic SRAF printing classification mechanism is essential to improve detection accuracy and efficiency. This paper presents a method of classifying SRAF printing based on a database-independent contour extraction algorithm. By size calculation on extracted contour SRAF feature printing classification can be made automatically. This flow has been demonstrated to be able to correctly classify SRAF printing with consistent performance thus avoid the subjectivity and inconsistency in human judgement.
CDSEM metrology is a powerful tool to obtain silicon data. However, as our technology nodes advance shrink to 14nm and below, the CD measurement data from CDSEM can hardly provide sufficient information for OPC verification (OPCV) and the related silicon verification. On the other hand, the abundant information from CDSEM images has not been fully utilized to assist our data analysis. In this context, contour extraction emerges as the best method to obtain extensive information from CDSEM images, especially for 2D structures. This paper demonstrates that contour extraction bridges the gap between the needs of 2D characterization and the limited capability of CDSEM measurement. The extracted contour enables automatic identification of litho-hotspots using OPCV tools, especially for non-CD related hotspots. Statistical silicon data extraction and analysis on complex geometries is viable with extracted contours. The silicon data can then be feedback to the evolution of non-CD OPCV checks, where simple CD measurement is inadequate. Effective CD can also be calculated from the obtained 2D information, with which Bossung curves can be built and provide complementary information.
The ever increasing pattern densities and design complexities make the tuning of optical proximity correction (OPC)
recipes more challenging. There are various recipe tuning methods to meet the challenge, such as genetic algorithm
(GA), simulated annealing, and OPC software vendor provided recipe optimizers. However, these methodologies usually
only consider edge placement errors (EPEs). Therefore, these techniques may not provide adequate freedom to solve
unique problems at special geometries, for example bridge, pinch, and process variation band related violations at
complex 2D geometries.
This paper introduces a general methodology to fix specific problems identified at the OPC verification stage and
demonstrates its successful application to two test-cases. The algorithm and method of the automatic scoring system is
introduced in order to identify and prioritize the problems that need to be fixed based on severity, with the POR recipe
score used as the baseline reference. A GA optimizer, whose objective function is based on the scoring system, is
applied to tune the OPC recipe parameters to optimum condition after generations of selections. The GA optimized
recipe would be compared to existing recipe to quantify the amount of improvement.
This technique was subsequently applied to eliminate certain chronic OPC verification problems which were
encountered in the past. Though the benefits have been demonstrated for limited test cases, employing this technique
more universally will enable users to efficiently reduce the number of OPC verification violations and provide robust