Supercapacitor is achieved by combining tin oxide with three dimensional silicon microchannel plates (Si-MCPs) deposited with nickel film. Electro deposition is applied to deposit the tin oxide on the Ni/Si-MCPs structure followed by sintering at 450°C. The structure and morphology of the samples are characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM). The electrochemical properties are investigated in 1 M Na2SO4 solution by cyclic voltammetry, galvanostatic charging-discharging, and electrochemical impedance spectroscopy. The highest specific capacitance of 0.814 F/cm2 (171.37 F/g) is achieved from the sample deposited for 2 h followed by sintering for 2 h.
By combining a SnO2 thin film with silicon dioxide microchannel plate (SiO2-MCP), a three-dimensional (3D) structure with enough space to accommodate the volume change of SnO2 during charging-discharging is produced by MEMS and electroless deposition. Owing to the special structure of the MCP, the battery is able to deliver a reversible Li storage capacity of 408 mAhg-1 after 100 cycles. If the current density is reduced to 200 mAg-1 at a constant current during charging and discharging, the battery exhibits reversible capacities of 1575 and 996 mAhg-1 in the first discharging and charging cycle, respectively. However, a reversible Li-storage capacity of only 298 mAhg−1 is obtained after 50 cycles of deep charging at a current of 200 mAg−1. It is found that silicon is involved in the charging-discharging process at a low current.
The influence of backside illumination and temperature on the fabrication of large and high aspect ratio silicon microchannel plates (MCPs) by photoelectrochemical (PEC) process is described. Backside illumination is provided by three 150-W tungsten halogen lamps with a feedback loop, keeping a constant current density. The etching temperature is maintained by a circulation system. Proper backside illumination and the lower temperature can provide better integrated etching conditions compared to that without illumination and temperature control. Etching under the improved conditions results in smoother undercutting and better surface topography for large (effective diameter of about 80 mm for 4-inch silicon substrates) silicon microchannel plates. Enhancing the backside illumination within the etching temperature range ensures that the aspect ratio is more than 40, boding well for applications of silicon microchannel plates.
The microelectromechanical variable optical attenuator (VOA) using an electrostatic beam combined with a fiber-optic
collimator has designed and fabricated. This VOA is based on silicon-on-insulator (SOI). When the driving voltage is
applied to the beam and the substrate, the beam will yield a vertical displacement. Then the reflected light can't enter
into the coupled fiber completely. Based on electrostatic actuation, the attenuation level is adjusted by changing the
displacement of the beam. The relationship between the voltage and the displacement was analyzed by using ANSYS, a
finite element analysis software package. The result of the simulation shows that the attenuator with the new structure
has good performances. The fabrication steps use two wet etching processes. The active layer of SOI wafer is first
patterned into the mirror sharp by TMAH, and the backside is etched to the buried oxide (BOX) using a 2-μm-thick SiO2
mask. After releasing the structure in hydrofluoric acid, gold layers are deposited by vacuum evaporation. The testing is
still in progress.
In this report, p-type macroporous silicon has been prepared by anodization. A phosphorus diffusion step is employed for
the formation of three dimensional pn junction structures on this macroporous silicon. I-V and C-V measurement were
employed to characterize the electrical properties. The results were compared with numeric simulation with T-SUPREM4
and MEDICI. It has been demonstrated that three-dimensional structure can increase the effective junction
area and the collective efficiency remarkably, and hence improve the performance of semiconductor radiation detector.
Fabrication of deep pores and trenches in nano-size will enable the embedded nanodevice integrated with silicon IC.
However, the conventional dry etching method needs very expensive equipment and the process is quite complicated.
Recently, electrochemical etching was developed to fabricate structures with high aspect ratio. Anodization was
performed in a solution of HF with certain concentration mixed with ethanol by 1:1 in volume. The backside of the wafer
was illuminated by a halogen lamp. The whole etching system was monitored by a computer system. It is found, in case
of etching in a low current with 5%HF electrolyte, the size etched pores can be less than 100 nm. However, the deep
trench structures becomes a line array of pores. Further work is in progress to investigate the detail.
The MEMS-type Fabry-Perot cavity is used widely in some kinds of tunable optical MEMS devices. In this paper, the index compatible problem of multi-layer optical film design of Fabry-Perot cavity in the variable optical attenuator (VOA) has been investigated, which is using the transport matrix of optical medium film theoretically. Based on our theoretical model and simulation, our design for the MEMS-type Fabry-Perot cavity has better advantage of the compatibility. At first, it can be adjusted for the different working mode. Secondly, the thickness of the multi-layer film can be restructured according the refractive index of the material available. Finally, it is a self-alignment system, which makes it quite favorable for fiber alignment and procedure of package.
In this paper, silicon nitride film, as thick as 1.1μm, was first deposited on porous silicon by plasma enhanced chemical vapor deposition (PECVD). No crack was detected, on the contrary of the case that is deposited on a single crystalline thin film. Such layer was bonded to a glass substrate via a media of optical epoxy. And finally, separation of such layer from the original silicon substrate via splitting of porous silicon was investigated and the transmission properties before and after transfer bonding process were investigated. It is shown that such a transfer bonding process can be a good solution to the attenuation problem in silicon based RF system.
Photo-assisted electrochemical etching is a newly developed technology for the deep etching process in silicon. The principle for such a process is based on the dissolution of silicon in a diluted HF strongly depends on the distribution of holes injection, so existence of tips lead to the electrochemical etching process along the vertical direction of the wafers. In this paper, the current-voltage characteristic of etching process and influence of temperature on the process of photo-assisted electrochemical etching process on silicon has been reported. In detail, the relationship between etching current and bias voltage in deferent region and the related mechanism, how does temperature influence this current-voltage characteristic have been explored. It is demonstrated that low temperature process and proper bias voltage is critical for the uniformity of PAECE process.
Thinning of micromachined wafers containing trenches and cavities to realize through-chip interconnects is presented. Successful thinning of wafers by lapping and polishing until the cavities previously etched by deep reactive ion etching are reached is demonstrated. The possible causes of damage to the etched structures are investigated. The trapping of particles in the cavities and suitable cleaning procedures to address this issue are studied. The results achieved so far allow further processing of the thinned wafers to form through wafer interconnections by copper electroplating. Further improvement of the quality of thinned surfaces can be achieved by alternative cleaning procedures.