For many years traditional 193i lithography has been extended to the next technology node by means of multi-patterning techniques. However recently such a 193i technology became challenging and expensive to push beyond the technology node for complex features that can be tackled in a simpler manner by the Extreme UltraViolet Lithography (EUVL) technology. Nowadays, EUVL is part of the high-volume manufacturing device landscape and it has reached a critical decision point where one can push further the single print on 0.33NA full field scanner or move to a EUV double patterning technology with more relaxed pitches to overcome current 0.33NA stochastic limits. In this work we have selected the 28nm pitch dense line-space (P28) as critical decision check point. We have looked at the 0.33NA EUV single print because it is more cost effective than 0.33NA EUV double patterning. In addition, we have conducted a process feasibility study as P28 in single print is close to the resolution limit of the 0.33NA EUV full field scanner. We present the process results on 28nm dense line-space patterning by using Inpria’s metal-oxide (MOx) EUV resist. We discuss the lithographic and etching process challenges by looking at resist sensitivity, unbiased line edge roughness (LER) and nano patterning failures after etching (AE), using broad band plasma (BBP) and e-beam (EB) defectivity inspection tools. To get further understanding on the P28 single patterning capability we have integrated the developed EUV MOx process in a relevant iN7 technology test vehicle by developing a full P28 metallization module with ruthenium. In such a way we were able to carry on electrical tests on metallized serpentine, fork-fork and tip-to-tip structures designed with a purpose of enabling further learning on pattern failures through electrical measurements. Finally, we conclude by showing the readiness of P28 single exposure using Inpria’s MOx process on a 0.33NA EUV full field scanner.
Self-Aligned Gate Contact (SAGC) integration is design based on formation of the two separate contacts to the source/drain (S/D) and to the gate (G), which are realized in two separate plasma etch steps. Essentially, the first one is the contact plug (CP) etch over S/D contact selective to the gate plug (GP) and sidewall spacer (SWS), and the second one is the gate plug (GP) etch selective to the contact plug (CP) and the sidewall spacer (SWS). Therefore, the high selectivity plasma etch processing for the CP and GP towards the other two relevant, neighboring films is a key requirement for successful SAGC integration. In this paper we present plasma etch process development required for SAGC implementation, primarily focusing on the multi-color selectivity studies, i.e., selective CP (towards GP and SWS) as well as selective GP (towards CP and SWS) at contacted poly pitch (CPP) 42nm. The primary (‘standard’) integration scheme uses SiO2 CP, Si3N4 GP and SiCO SWS. Furthermore, we investigate the “alternative’ integration scheme with SiCxNy films as replacement of the traditionally used SiO2 CP material aiming to simplify the patterning sequence and ease high selectivity requirements. We report the selectivity values obtained on the CP/GP/SWS multi-color stack for the CP plasma processing (SiO2 or SiCxNy) towards Si3N4 and SiCO; as well as for GP (Si3N4) plasma dry etch process towards SiO2 or SiCxNy and SiCO. Using a Quasi-ALE (Q-ALE) approach for selective SiO2 etch process is developed with a selectivity of 8 to 1 towards Si3N4 and SiCO. For the selective Si3N4 etch continuous wave plasma CH3F-based process is developed and selectivity of 9 to 1 towards SiO2 and SiCO achieved. In the case of the integration scheme with SiCxNy CP, the selectivity for SiCxNy etch towards Si3N4 GP and SiCO SWS higher than 20 to 1 is accomplished using continuous RF source NF3/O2- based process. As for the Si3N4 plasma etch in the ‘alternative’ scheme using CH3F/O2-based process, the selectivity towards SiCxNy of higher than 20 to 1 and selectivity to SiCO of around 10 to 1 is achieved.
With increasing challenges in reducing power density while keeping and even increasing the device performance at every new technology node, innovations in both the device architecture and materials will be needed to ensure continuous improvements in power, performance, area and cost. For the last decade, replacing the Si channel by higher mobility materials like III-V and (Si)Ge has been considered as one of the most challenging innovations needed to further scale down the supply voltage and improve the overall energy efficiency of CMOS circuits. While these materials will not only contribute to enhancing the standard CMOS performance, the possibility of integrating these materials on a Si platform opens exciting new opportunities to build unique circuits, systems and applications. Especially in RF applications, co-integration of III-V/GaN and Si CMOS might be the key enabling technology to provide the speed and power efficiency required for next generation mobile communications. While the device architectures under consideration differ from nowadays ultra-scaled FinFET and nanowire/nanosheet technologies, and their scaling in general is more relaxed, there are significant challenges related to integrating these components on Si substrates. It will need innovations in patterning, deposition and cleaning, next to addressing the challenges of handling these novel materials in a standard CMOS environment. In this work, we will review the status and integration challenges of these materials for both advanced CMOS technologies and RF applications. Focus will be put on the required advancements in etch and deposition needed to enable the integration of these novel materials and devices on a Si platform.