This paper reports the water-leakage mechanism of the immersion hood in an immersion scanner. The proposed static
analysis reveals the immersion hood design performance in defect distribution. A dynamic water-leakage model traces
the leaked water and identifies its position on the wafer, during exposure. Comparing simulation to experimental results
on bare-silicon and resist-coated wafers, the defect type, source of residuals, and critical settings on the immersion
system were clearly identified.
193-nm immersion lithography is the only choice for the 45-nm logical node at 120-nm half pitch and extendable to 32-
and 22-nm nodes. The defect problem is one of the critical issues in immersion technology. In this paper, we provided a
methodology to trace the defect source from optical microscope images to its SEM counterparts after exposure. An
optimized exposure routing was also proposed to reduce printing defects. The average defect count was reduced from
19.7 to 4.8 ea/wafer.
This letter reports record-breaking low defect counts for immersion lithography, the mechanism for formation of particle-printing defects, and for two new exposure routings to achieve the low defect counts. Both new routings make the slot-scan directions parallel to the field-stepping directions, whereas in the normal routing the two directions are perpendicular to each other. From experimental data, the average defect count for one of the special routings is 4.8 per wafer, while it is 19.7 per wafer for normal routing.
The non-paraxial correction term of high-NA effect was studied for scalar field in optical microlithography. However, the correction term of scalar field should be modified for vector field. Based on a thin mask, the characteristic of vector field can be described with the Symthe-Kirchhoff formula. The non-paraxial correction term of vector field can be derived with the combination of both the law of energy conservation and sine condition on entrance pupil and exit pupil. The correction term of vector field depends on the degree of polarization of incident light. As the result, the correction term of TE wave of vector field is the same characteristic as that of scalar field. However, the correction term of TM wave of vector is different from that of scalar field.
ArF immersion lithography is essential to extend optical lithography. In this study, we characterized the immersion process on production wafers. Key lithographic manufacturing parameters, overlay, CD uniformity, depth of focus (DOF), optical proximity effects (OPE), and defects are reported. Similar device electrical performance between the immersion and the dry wafers assures electrical compatibility with immersion lithography. The yield results on 90-nm Static Random Access Memory (SRAM) chips confirm doubling of DOF by immersion as expected. Poly images of the 65-nm node from a 0.85NA immersion scanner are also shown.
This paper presented an integrated simulation framework linking our in-house mask writer simulator and the optical lithography simulation engines to include the mask corner rounding effect in lithographic performance evaluations. In the writer simulator, a modified two-dimensional Gaussian function is used as the functional form of the convolution kernel (point spread function). Parameters of the kernel function for different writing machines are automatically extracted from scanning electron microscope (SEM) photographs of simple mask pattern geometries. The convolution results of the kernel and the mask layout form the intensity distribution for pattern definition. The isocontour of the resulting image at the desired level of bias can be regarded as a good approximation of the mask shape obtained from a real mask writer. The writer simulator then saves the contour data as the user-specified format of mask file for subsequent lithography simulations. With the aid of this simulation tool, the impacts of mask corner rounding effects on two-dimensional OPCed pattern for 90-nm and 65-nm node lithography processes are quantitatively evaluated. The results show the line end shortening (LES) is greatly influenced by mask corner rounding effects. The LESs in the 65-nm node process are over twice of those in the 90-nm node process. The resolution capability of a 2-stage 16X mask manufacturing process was also studied in this paper. Simulation results indicate the ArF lithography might be required to make this innovative mask-making technology suitable for 90-nm generation and beyond.
This paper introduces the continuous wavelet transform (CWT) techniques to characterize spatial frequencies of LER. A 890 nm length of line pattern was dissected with 448 measured-points along line-edge from the image of scanning electron microscope (SEM), and the dissection of measurement points is around 2 nm. The measured data of line-edge roughness (LER) were transformed to spatial power spectrum with commercial software packages of wavelet transform, and the characterization of spatial frequency correlated to lithographic process parameters, such as the soft-bake (SB) temperature, the numerical aperture (NA), the temperature of post-exposure baking (PEB), and the molecular weight of resist (MW) were investigated. The higher NA and lower SB give a significant improvement from low spatial frequency (long range LER) to higher one (short range LER). However, both the higher temperature of PEB and lower MW improve edge roughness only on long range order roughness (lower spatial frequency).
The present paper demonstrates the applicability of thermal flow resist to print sub-0.1micrometers contact holes using 248nm lithography. With the thermal flow resist, 200nm contact holes were defined by KrF lithography system. Then following one step thermal flow resulted in down to 70nm contact holes with vertical sidewall profile. The main feature of the thermal flow resist is one step process having the linear dependency of flow rate on baking temperature. As the results, thermal flow resists pattern shrinkage controlled by post development baking temperature. Resist flowing occurred post development temperature was higher than Tg. Baking temperature was not the dominant factor from the contact hole shrinkage size curve. The thermal flow process using the thermal flow resist is a promising candidate for the fabrication of gigabit devices.
In an attempt to develop the dual damascene process in 0.13 micrometer design rule, the trench optics, resist usage, reflectivity control and BARC strategy for 0.18 micrometer S/L on 0.20 micrometer via dual damascene process are discussed. The difficulty of 0.18 micrometer trench process will be concentrated by two reasons: First, the trench optics is totally different from the traditional L/S patterns either observing the pupil plane wave vector or the aerial image versus defocus, it contains the intrinsic limitation to drive and enough process DOF. Secondly, the PR residues remain in via due to the weak light incidence into via as soon as trench exposure. The side issues are the MEEF problem in dark field exposure and lens aberration problem enhanced in the use of PSM or some kinds of special customized illumination filter CIFs. As a result, the negative resist together with NA equals 0.55, (sigma) equals 0.8, annular 1/2 illumination were applied, it reveals that all mentioned issues are properly compromised by this optimized condition. It is also found that the PR window and profile is quite sensitive to substrate acidity and reflectivity. When BARC protecting coating and reflectivity control problems are taken into account simultaneously, the thin conformal BARC and fully filled polymer on dual SiO<SUB>X</SUB>N<SUB>Y</SUB> underlayer are introduced to get a good profile and CD control. Experimental results exhibit the feasibility in manufacturing.
High NA illumination system and off-axis illumination (OAI) have been shown as two of the most practical resolution enhancement techniques (RET) available for micro-lithography. However, these two illumination approaches may reduce the DOF of iso-patterns. To overcome this problem, scattering bar (SB) assignment has been wildly used. In this paper, the discussions are focused on SB variables of iso-features. The most important variable of SB usage is where is the suitable assignment position. A simply efficient rule has been found to easily catch the optimal position of SB assignment. For OAI illumination, the optimal SB position is exactly the same with the defocus side-lobe position of iso-line. The effect of the secondary pair of SB is also discussed in this paper, and it is found that if the secondary SB pair was not at the optimal position, the process window would be reduced. Another major topic in this paper is the specification of SB width. Here we design a test pattern to target the specification of SB width. The experimental results might give us a clear specification of SB width.
A great deal of progress has been made in the design of dual damascene process, including via first, trench first, and self-aligned. For overlay, via-first process provides the largest process tolerance to misalignment. However, the positive tone resist face to some difficulties in dual damascene via first approach of photo process, because the 0.18micrometers positive tone trench resist can not be exposed and removed in the 0.20micrometers via hole, observed residues from the SEM cross section profiles after development. In contrast, the negative tone resist show s great advantage in the via first process and producing desired patterns without resist residues in the via hole. In this paper, the design of dual damascene photo process using commercial N702Y (JSR) negative tone resist on DUV43 (Brewer Sc.) Bottom anti reflective coating is evaluated. To improve the depth of focus (DOF) of negative tone resist process, the different resolution enhancement techniques (RET) are investigated fro dense and isolated trench patterns: off-axis illumination (annular ½), attenuated phase shift mask (halftone 6%) with 248nm (NA 0.55) exposure technology, and experimental results regarding to its process performance are presented.