The backside of photomasks have been largely ignored during the last several decades of development, with the exception of avoiding gross damage or defects, as almost all problems are far enough out of the focal plane to have minimal effect on imaging. Since EUV masks are reflective, and the column is held in a vacuum, scanners have been designed to utilize electrostatic chucking. With the chucking system for EUV, the requirements for the backside of the mask must be redefined to integrate concerns in substrate design, mask manufacturing, and usage. The two key concerns with respect to an electrostatic chuck are defects and durability. Backside defects can affect imaging, while potentially damaging or contaminating the tool, the mask, or even subsequently used masks. Compromised durability, from either usage or cleaning, can affect the ability of the chuck to hold the mask in place. In this study, these concerns are evaluated in three stages: minimizing defects created during mask fabrication, actions taken upon discovery of defects, and durability of the backside film with continued cleans and chucking. Data incorporated in this study includes: sheet resistance, film thickness, and optical inspection images. Incorporating the data from the three stages of fabrication, disposition, and lifetime will help us define how to structure backside EUV mask handling during mask manufacture and indicate what further solutions are needed as EUV technology transitions into manufacturing.
The cleaning requirements for EUV masks are more complex than optical masks due to the absence of available EUVcompatible pellicles. EUV masks must therefore be capable of undergoing more than 100 cleaning cycles with minimum impact to lithographic performance. EUV masks are created on substrates with 40 multilayers of silicon and molybdenum to form a Bragg reflector, capped with a 2.5nm-thick ruthenium layer and a tantalum-based absorber; during usage, both ruthenium and absorber are exposed to the cleaning process. The CrN layer on the backside is used to enable electrostatic clamping. This clamp side must also be free of particles that could impact printing and overlay, and particles could also potentially migrate to the frontside and create defects. Thus, the cleaning process must provide decent particle removal efficiencies on both front- and backside while maintaining reflectivity with minimal surface roughness change. In this paper, we report progress developing a concurrent patterned-side and clamped-side cleaning process that achieves minimal reflectivity change over 120 cleaning cycles, with XPS and EDS indicating the presence of ruthenium after 125 cleaning cycles. The change in surface roughness over 100 cleaning cycles is within the noise (0.0086nm) on a mask blank, and SEM inspection of 100nm and 200nm features on patterned masks after undergoing 100 cleaning cycles show no indications of ruthenium pitting or significant surface damage. This process was used on test masks to remove particles from both sides that would otherwise inhibit these masks from being used in the scanner.
The successful demonstration of 637 wafer exposures in 24 hours on the EUV scanner at the IBM EUV Center for
Excellence in July marked the transition from research to process development using EUV lithography. Early process
development on a new tool involves significant characterization, as it is necessary to benchmark tool performance and
process capability. This work highlights some key learning from early EUV process development with a focus on
identifying the largest sources of variability for trench and via hole patterning through the patterning process. The EUV
scanner demonstrated stable overlay on a 40 lot test run using integrated wafers. The within field and local critical
dimension uniformity (CDU) are the largest contributors to CD variations. The line edge roughness (LER) and line
width roughness (LWR) in EUV resist will be compared to the post etch value to determine the effect of processing.
While these numbers are generally used to describe the robustness of 1D trenches or circular vias, the need to accurately
evaluate the printability of irregular 2D features has become increasingly important. In the past 5 years, models built
from critical dimension scanning electron microscope (CDSEM) contours has become a hot topic in computational
lithography. Applying this methodology, the CDSEM contour technique will be used to assess the uniformity of these
irregular patterns in EUV resist and after etching. CDSEM contours also have additional benefits for via pattern
Thermal Scanning Probe Lithography (tSPL) is an AFM based patterning technique, which uses heated tips to locally evaporate organic resists such as molecular glasses  or thermally sensitive polymers. Organic resists offer the versatility of the lithography process known from the CMOS environment and simultaneously ensure a highly stable and low wear tip-sample contact due to the soft nature of the resists. Patterning quality is excellent up to a resolution of sub 15 nm, at linear speeds of up to 20 mm/s and pixel rates of up to 500 kHz. The patterning depth is proportional to the applied force which allows for the creation of 3-D profiles in a single patterning run. In addition, non-destructive imaging can be done at pixel rates of more than 500 kHz. If the thermal stimulus for writing the pattern is switched off the same tip can be used to record the written topography with Angstrom depth resolution. We utilize this unique feature of SPL to implement an efficient control system for reliable patterning at high speed and high resolution. We combine the writing and imaging process in a single raster scan of the surface. In this closed loop lithography (CLL) approach, we use the acquired data to optimize the writing parameters on the fly. Excellent control is in particular important for an accurate reproduction of complex 3D patterns. These novel patterning capabilities are equally important for a high quality transfer of two-dimensional patterns into the underlying substrate. We utilize an only 3-4 nm thick SiOx hardmask to amplify the 8±0.5 nm deep patterns created by tSPL into a 50 nm thick transfer polymer. The structures in the transfer polymer can be used to create metallic lines by a lift-off process or to further process the pattern into the substrate. Here we demonstrate the fabrication of 27 nm wide lines and trenches 60 nm deep into the Silicon substrate. In addition, the combined read and write approach ensures that the lateral offset between read and write field is minimized. Thus we achieve high precision in marker-less stitching of patterning fields. A 2D cross-correlation technique is used to determine the offset of a neighboring patterning field relative to a previously written field with an accuracy of about 1 nm. We demonstrate stitching of 1 μm2 fields with ~5 nm accuracy and stitching of larger 10x10 μm2 fields with 10 nm accuracy.
Heated tips offer the possibility to create arbitrary high-resolution nanostructures by local decomposition and
evaporation of resist materials. Turnaround times of minutes are achieved with this patterning method due to the high-speed
direct-write process and an in-situ imaging capability. Dense features with 10 nm half-pitch can be written into
thin films of organic resists such as self-amplified depolymerization (SAD) polymers or molecular glasses. The
patterning speed of tSPL has been increased far beyond usual scanning probe lithography (SPL) technologies and
approaches the speed of Gaussian shaped electron beam lithography (EBL) for <30 nm resolution. A single tip can write
complex patterns with a pixel rate of 500 kHz and a linear scan speed of 20 mm/s. Moreover, a novel scheme for
stitching was developed to extend the patterning area beyond the ≤100 μm range of the piezo stages. A stitching
accuracy of 10 nm is obtained without the use of markers. Furthermore, the patterning depth can be controlled
independently and accurately (~1 nm) at each position. Thereby, arbitrary 3D structures can be written in a single step.
Finally, we demonstrated an all-dry tri-layer pattern transfer concept to create high aspect ratio structures in silicon.
Dense fins and trenches with 27 nm half-pitch and a line edge roughness (LER) below 3nm (3σ) have been fabricated.