The SPADnet FP7 European project is aimed at a new generation of fully digital, scalable and networked photonic components to enable large area image sensors, with primary target gamma-ray and coincidence detection in (Time-of- Flight) Positron Emission Tomography (PET). SPADnet relies on standard CMOS technology, therefore allowing for MRI compatibility. SPADnet innovates in several areas of PET systems, from optical coupling to single-photon sensor architectures, from intelligent ring networks to reconstruction algorithms. It is built around a natively digital, intelligent SPAD (Single-Photon Avalanche Diode)-based sensor device which comprises an array of 8×16 pixels, each composed of 4 mini-SiPMs with in situ time-to-digital conversion, a multi-ring network to filter, carry, and process data produced by the sensors at 2Gbps, and a 130nm CMOS process enabling mass-production of photonic modules that are optically interfaced to scintillator crystals. A few tens of sensor devices are tightly abutted on a single PCB to form a so-called sensor tile, thanks to TSV (Through Silicon Via) connections to their backside (replacing conventional wire bonding). The sensor tile is in turn interfaced to an FPGA-based PCB on its back. The resulting photonic module acts as an autonomous sensing and computing unit, individually detecting gamma photons as well as thermal and Compton events. It determines in real time basic information for each scintillation event, such as exact time of arrival, position and energy, and communicates it to its peers in the field of view. Coincidence detection does therefore occur directly in the ring itself, in a differed and distributed manner to ensure scalability. The selected true coincidence events are then collected by a snooper module, from which they are transferred to an external reconstruction computer using Gigabit Ethernet.
A family of scaleable single photon avalanche diode (SPAD) structures in 130nm and 90nm CMOS is presented.
Performance trends such as dark count rate (DCR), jitter and breakdown voltage are studied versus active diameter for
devices ranging from 32μm down to 2μm. To address pixel pitch we introduce a shared buried n-well approach allowing
compact arrays containing both NMOS-transistor readout circuitry and SPAD devices. A pixel pitch of 5μm has been
achieved in 90nm CMOS technology, offering the potential for future megapixel single photon image sensors.
The first implementation of a single photon avalanche diode (SPAD) is reported in 130nm CMOS technology. The
SPAD is fabricated as p+/nwell junction with octagonal shape. Premature edge breakdown is prevented through a guard
ring of p-well around the p+ anode. The dynamics of the new device are investigated using both active and passive
quenching methods. Single photon detection is achieved by sensing the avalanche using a fast comparator. The SPAD
exhibits a maximum photon detection probability of 41% and a typical dark count rate of 100kHz at room temperature.
Thanks to its timing resolution of 144ps (FWHM), the SPAD can be used in disparate disciplines, including medical
imaging, 3D vision, biophotonics, low-light-illumination imaging, etc.
CMOS imagers are commonly employing pinned photodiode pixels and true correlated double sampling to eliminate kTC noise and achieve low noise performance. Low noise performance also depends on optimisation of the readout circuitry. This paper investigates the effect of the pixel source follower transistor on the overall noise performance through several characterization methods. The characterization methods are described, and experimental results are detailed. It is shown that the source follower noise can be the limiting factor of the image sensor and requires optimisation.