Up to now, there is no direct test system of current pulse in phase change memory (PCM). The traditional test system uses direct current or voltage pulses to do the set operation and voltage pulses to do reset operation. In this work, a new test system is introduced. This system can give current source pulses to the PCM device to do set operation. The test results are presented and analyzed.
An 8Mb phase change random access memory (PCRAM) has been developed by a 130nm 4-ML standard CMOS technology based on the Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2V NMOS device. Aimed at the resistance distributions, lowering the operation current and improving the bit yield, some methods are used to optimize the design of the chip.
Resistance distributions of the crystalline (SET) state and amorphous (RESET) state for phase change memory (PCM) are experimentally investigated at the array level. The RESET distribution shows a low resistance tail, which potentially affects the reading margin of the chip. These tail cells are divided into two types by resistance programming current (R-IP) and current voltage (I-V) characteristics. Finally, approaches of improving the integration process to remove the Type-1 tail cells and optimizing the programming operation to repair the Type-2 tail cells are proposed.