Chemical-mechanical polishing (CMP) is a key process in integrated circuit (IC) manufacturing. Successful fabrication of semiconductor devices is highly dependent on the final planarity of the processed layers. Post-CMP topography variation may cause degradation of the circuit performance. Moreover, the depth-of-focus (DOF) requirement is critical for lithography of subsequent layers. As such, planarity requirements are critical for maintaining IC manufacturing technology scaling trends, and supporting device innovation. To mitigate post-CMP planarity issues, dummy fill insertion has become a commonly-used technique. Many factors impact dummy fill insertion results, including fill shapes, sizes, and the spacing between both fill shapes and the drawn layout patterns. The goal of the CMP engineer is to optimize design planarity, but the variety of fill options means just verifying the design rules for fill is a challenging task. This data collection currently requires a long development cycle, consuming a great deal of time and resources. In this paper, we show how CMP modeling can help resolve these issues by applying CMP modeling and simulations to drive Calibre YieldEnhancer SmartFill parameters that have been optimized for dummy fill. Additional capabilities in the SmartFill functionality automate CMP hotspot fixing steps. Using CMP simulations, engineers can get feedback about post-CMP planarity for given fill options in a much shorter time. Not only does this move dummy fill optimization experiments from a real lab into a virtual lab of CMP modeling and simulation, but it also provides more time for these experiments, providing improved results.