The transport properties of GaN and its alloys are attracting increasing interest due to the potential application of these
materials for solar blind photodetectors and high mobility transistors. Because of the large band gap, the applications of
AlxGa1−xN are extensive, such as for visible-blind ultraviolet detectors, laser diodes, and short-wave light emitting diodes
(LEDs). However, the persistent photoconductivity (PPC) of GaN based photoconductive devices affects its applications.
In order to study the origin of PPC, we designed solar blind ultraviolet photoconductive detector, which consists of n -
Al0.65Ga0.35N top contact layer (100nm), n-Al0.42Ga0.58N/i-Al0.65Ga0.35N superlattice layers (200nm), i- Al0.65Ga0.35N layer
(600nm), AlN buffer layer and double polished sapphire substrate. Moreover, there are photoconductive devices with
different photosensitive areas. Investigations of electric-field effects and thermal effects on PPC in
n-Al0.42Ga0.58N/i-Al0.65Ga0.35N superlattice are presented. We have observed that, by applying a high-voltage pulse, the
course of PPC was effectively accelerated: With the same pulse width and different voltage, in the appropriate range, the
higher of the voltage, the course of PPC was more effectively accelerated; with the same voltage and different pulse
width, in the appropriate range, the wider of the pulse width, the course of PPC was more effectively accelerated. And
PPC effect strongly depends on the temperature. The decay time of the PPC depend on the temperature and become
longer with a decreasing temperature.
CdZnTe is the most suitable epitaxial substrate material of HgCdTe infrared detectors, because its lattice constant is able to achieve full match with HgCdTe’s lattice constant. It is always needed to etch CdZnTe substrate during the process of device separation or when we want to fabricate micro optical device on CdZnTe substrate. This paper adopts the more advanced method, Inductive Coupled Plasma-Reactive Ion Etching(ICP-RIE). The etching conditions of ICP-RIE on CdZnTe substrate are explored and researched. First of all, a set of comparative experiments is designed. All of CdZnTe samples with the same component are polished by chemical mechanical polishing before etching. Then all samples are etched by different types of etching gases(CH4/H2/N2/Ar) and different ratios of gases as we designed. The etching time is all set to 30 minutes. After that, the surface roughness, etching rate, etching damage and the profile of etched mesas are tested and characterized by optical microscope, step profiler and confocal laser scanning microscope (CLSM), respectively. It is found that, Ar gas plays the role of physical etching, but the etching rate will decline when the concentration of Ar gas is too high. The results also show that, the introduction of N2 causes more etching damage. Finally, combination of CH4/H2/Ar is used to etch CdZnTe substrate. The ratio of these gases is 2sccm/2sccm/10sccm. The testing results of optimized etching show that, the maximum etching rate reaches up to 20μm/h and the etched CdZnTe surface is smooth with very low etching damage. At last, aimed at the shortcoming of photoresist’s degeneration after long-time etching, the ICP etching process of CdZnTe deep mesa is studied. Double-layer or triple-layer photoresist are spin-coated on CdZnTe substrate during the process of lithography. Then ICP etching is carried out with the optimized condition. It is seen that there is no more phenomena of degeneration.
Electrochemical Capacitance-Voltage (EC-V) profiling is currently one of the most often used methods for majority carrier concentration depth profiling of semiconductors. The experiments of EC-V profiling on InP based structures were conducted by Wafer Profiler CVP21, and there are two problems in the experiments of InP based p-i-n structures : a）the experimental results of EC-V profiling of i layer were not in line with the theoretically data after the EC-V profiling of p layer, which can be measured within the error range; b) The measurements of etching depth were not very accurate. In this paper, we made comparative experiments on InP based n-i-n structures, and find out a method to deal with the first problem: firstly etch p layer before EC-V profiling, so we can gain a relatively accurate result of EC-V profiling of i layer. Besides, use back contacts instead of front contacts to do the EC-V profiling according to the instruction book of the Wafer Profiler CVP21. Then the author tried to infer the reason that results in the first problem theoretically. Meanwhile we can calibrate the etching depth through Profile-system and Scanning Probe Microscope (SPM). And there are two possible reasons which result in the second problem: the defects of the semiconductors and the electrolyte we used to etch the semiconductors.